68 lines
1.9 KiB
Tcl
68 lines
1.9 KiB
Tcl
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_ad5766
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adi_ip_files axi_ad5766 [list \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/sync_bits.v" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/up_dac_common.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/util_pulse_gen.v" \
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"up_ad5766_sequencer.v" \
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"axi_ad5766.v" ]
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adi_ip_properties axi_ad5766
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adi_add_bus "spi_engine_ctrl" "master" \
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"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
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"analog.com:interface:spi_engine_ctrl:1.0" \
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{
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{"cmd_ready" "CMD_READY"} \
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{"cmd_valid" "CMD_VALID"} \
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{"cmd_data" "CMD_DATA"} \
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{"sdo_data_ready" "SDO_READY"} \
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{"sdo_data_valid" "SDO_VALID"} \
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{"sdo_data" "SDO_DATA"} \
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{"sdi_data_ready" "SDI_READY"} \
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{"sdi_data_valid" "SDI_VALID"} \
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{"sdi_data" "SDI_DATA"} \
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{"sync_ready" "SYNC_READY"} \
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{"sync_valid" "SYNC_VALID"} \
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{"sync_data" "SYNC_DATA"} \
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}
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adi_add_bus "spi_engine_offload_ctrl" "slave" \
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"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
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"analog.com:interface:spi_engine_offload_ctrl:1.0" \
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{ \
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{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
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{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
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{ "ctrl_enable" "ENABLE"} \
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{ "ctrl_enabled" "ENABLED"} \
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{ "ctrl_mem_reset" "MEM_RESET"} \
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}
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adi_add_bus "dma_fifo_tx" "master" \
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"analog.com:interface:fifo_rd_rtl:1.1" \
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"analog.com:interface:fifo_rd:1.1" \
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{ \
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{ "dma_data" "DATA"} \
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{ "dma_valid" "ENABLE"} \
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{ "dma_enable" "VALID"} \
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{ "dma_underflow" "UNDERFLOW"} \
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{ "dma_xfer_req" "XFER_REQ"} \
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}
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adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
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adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
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adi_add_bus_clock "dma_clk" "dma_fifo_tx"
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ipx::save_core [ipx::current_core]
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