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pluto_hdl_adi/projects/adrv9371x/common/adrv9371x_bd.tcl

300 lines
15 KiB
Tcl
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adrv9371x- added
2016-05-20 15:46:25 +00:00
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
adrv9371x- added
2016-05-20 15:46:25 +00:00
# ad9371
create_bd_port -dir I dac_fifo_bypass
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
# dac peripherals
adrv9371x- added
2016-05-20 15:46:25 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_clkgen axi_ad9371_tx_clkgen
ad_ip_parameter axi_ad9371_tx_clkgen CONFIG.ID 2
ad_ip_parameter axi_ad9371_tx_clkgen CONFIG.CLKIN_PERIOD 8
ad_ip_parameter axi_ad9371_tx_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter axi_ad9371_tx_clkgen CONFIG.VCO_MUL 8
ad_ip_parameter axi_ad9371_tx_clkgen CONFIG.CLK0_DIV 8
ad_ip_instance axi_adxcvr axi_ad9371_tx_xcvr
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.TX_OR_RX_N 1
adrv9371x: Set up the defualt clock output control The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default. The OUTCLK frequency is the same as the REFCLK. The main reason of this modification is that the links should come up without any DPR access, after power up, using the default reference clock configuration (122.88 MHz).
2018-03-22 13:17:24 +00:00
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.OUT_CLK_SEL 3
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.LPM_OR_DFE_N 0
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
adi_axi_jesd204_tx_create axi_ad9371_tx_jesd 4
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance util_upack util_ad9371_tx_upack
ad_ip_parameter util_ad9371_tx_upack CONFIG.CHANNEL_DATA_WIDTH 32
ad_ip_parameter util_ad9371_tx_upack CONFIG.NUM_OF_CHANNELS 4
ad_ip_instance axi_dmac axi_ad9371_tx_dma
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9371_tx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
adrv9371x- added
2016-05-20 15:46:25 +00:00
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
# adc peripherals
adrv9371x- added
2016-05-20 15:46:25 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_clkgen axi_ad9371_rx_clkgen
ad_ip_parameter axi_ad9371_rx_clkgen CONFIG.ID 2
ad_ip_parameter axi_ad9371_rx_clkgen CONFIG.CLKIN_PERIOD 8
ad_ip_parameter axi_ad9371_rx_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter axi_ad9371_rx_clkgen CONFIG.VCO_MUL 8
ad_ip_parameter axi_ad9371_rx_clkgen CONFIG.CLK0_DIV 8
ad_ip_instance axi_adxcvr axi_ad9371_rx_xcvr
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.TX_OR_RX_N 0
adrv9371x: Set up the defualt clock output control The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default. The OUTCLK frequency is the same as the REFCLK. The main reason of this modification is that the links should come up without any DPR access, after power up, using the default reference clock configuration (122.88 MHz).
2018-03-22 13:17:24 +00:00
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.OUT_CLK_SEL 3
ad_ip_parameter axi_ad9371_rx_xcvr CONFIG.LPM_OR_DFE_N 1
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
adi_axi_jesd204_rx_create axi_ad9371_rx_jesd 2
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance util_cpack util_ad9371_rx_cpack
ad_ip_parameter util_ad9371_rx_cpack CONFIG.CHANNEL_DATA_WIDTH 16
ad_ip_parameter util_ad9371_rx_cpack CONFIG.NUM_OF_CHANNELS 4
ad_ip_instance axi_dmac axi_ad9371_rx_dma
ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9371_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9371_rx_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9371_rx_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9371_rx_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9371_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_ad9371_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_ad9371_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
adrv9371x- added
2016-05-20 15:46:25 +00:00
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
# adc-os peripherals
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_clkgen axi_ad9371_rx_os_clkgen
ad_ip_parameter axi_ad9371_rx_os_clkgen CONFIG.ID 2
ad_ip_parameter axi_ad9371_rx_os_clkgen CONFIG.CLKIN_PERIOD 8
ad_ip_parameter axi_ad9371_rx_os_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter axi_ad9371_rx_os_clkgen CONFIG.VCO_MUL 8
ad_ip_parameter axi_ad9371_rx_os_clkgen CONFIG.CLK0_DIV 8
ad_ip_instance axi_adxcvr axi_ad9371_rx_os_xcvr
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.TX_OR_RX_N 0
adrv9371x: Set up the defualt clock output control The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default. The OUTCLK frequency is the same as the REFCLK. The main reason of this modification is that the links should come up without any DPR access, after power up, using the default reference clock configuration (122.88 MHz).
2018-03-22 13:17:24 +00:00
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.OUT_CLK_SEL 3
ad_ip_parameter axi_ad9371_rx_os_xcvr CONFIG.LPM_OR_DFE_N 1
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
adi_axi_jesd204_rx_create axi_ad9371_rx_os_jesd 2
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance util_cpack util_ad9371_rx_os_cpack
ad_ip_parameter util_ad9371_rx_os_cpack CONFIG.CHANNEL_DATA_WIDTH 32
ad_ip_parameter util_ad9371_rx_os_cpack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_dmac axi_ad9371_rx_os_dma
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC 64
adrv9371x- added
2016-05-20 15:46:25 +00:00
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
# common cores
adrv9371x- added
2016-05-20 15:46:25 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_ad9371 axi_ad9371_core
adrv9371x- added
2016-05-20 15:46:25 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance util_adxcvr util_ad9371_xcvr
ad_ip_parameter util_ad9371_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_ad9371_xcvr CONFIG.TX_NUM_OF_LANES 4
ad_ip_parameter util_ad9371_xcvr CONFIG.TX_OUT_DIV 2
ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_ad9371_xcvr CONFIG.RX_CLK25_DIV 5
ad_ip_parameter util_ad9371_xcvr CONFIG.TX_CLK25_DIV 5
ad_ip_parameter util_ad9371_xcvr CONFIG.RX_PMA_CFG 0x00018480
ad_ip_parameter util_ad9371_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020
adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary
2017-07-14 07:20:57 +00:00
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 0x120
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
# xcvr interfaces
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
create_bd_port -dir I rx_ref_clk_2
ad_xcvrpll tx_ref_clk_0 util_ad9371_xcvr/qpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_ad9371_xcvr/cpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_ad9371_xcvr/cpll_ref_clk_1
ad_xcvrpll rx_ref_clk_2 util_ad9371_xcvr/cpll_ref_clk_2
ad_xcvrpll rx_ref_clk_2 util_ad9371_xcvr/cpll_ref_clk_3
ad_xcvrpll axi_ad9371_tx_xcvr/up_pll_rst util_ad9371_xcvr/up_qpll_rst_0
ad_xcvrpll axi_ad9371_rx_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_0
ad_xcvrpll axi_ad9371_rx_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_1
ad_xcvrpll axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_2
ad_xcvrpll axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_3
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect sys_cpu_resetn util_ad9371_xcvr/up_rstn
ad_connect sys_cpu_clk util_ad9371_xcvr/up_clk
ad_xcvrcon util_ad9371_xcvr axi_ad9371_tx_xcvr axi_ad9371_tx_jesd
ad_reconct util_ad9371_xcvr/tx_out_clk_0 axi_ad9371_tx_clkgen/clk
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_0
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_1
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_2
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_3
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd/device_clk
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd_rstgen/slowest_sync_clk
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_reconct util_ad9371_xcvr/tx_0 axi_ad9371_tx_jesd/tx_phy3
ad_reconct util_ad9371_xcvr/tx_1 axi_ad9371_tx_jesd/tx_phy0
ad_reconct util_ad9371_xcvr/tx_2 axi_ad9371_tx_jesd/tx_phy1
ad_reconct util_ad9371_xcvr/tx_3 axi_ad9371_tx_jesd/tx_phy2
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_xcvr axi_ad9371_rx_jesd
ad_reconct util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_0
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_1
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd/device_clk
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd_rstgen/slowest_sync_clk
ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd
ad_reconct util_ad9371_xcvr/rx_out_clk_2 axi_ad9371_rx_os_clkgen/clk
ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_2
ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_3
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/device_clk
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd_rstgen/slowest_sync_clk
# dma clock & reset
adrv9371x- added
2016-05-20 15:46:25 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance proc_sys_reset sys_dma_rstgen
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen
2017-08-22 08:12:54 +00:00
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
ad_connect sys_dma_reset axi_ad9371_dacfifo/dma_rst
adrv9371x- added
2016-05-20 15:46:25 +00:00
# connections (dac)
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_connect axi_ad9371_tx_jesd/tx_data_tdata axi_ad9371_core/dac_tx_data
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_connect axi_ad9371_core/dac_valid_i0 util_ad9371_tx_upack/dac_valid_0
ad_connect axi_ad9371_core/dac_enable_i0 util_ad9371_tx_upack/dac_enable_0
ad_connect axi_ad9371_core/dac_data_i0 util_ad9371_tx_upack/dac_data_0
ad_connect axi_ad9371_core/dac_valid_q0 util_ad9371_tx_upack/dac_valid_1
ad_connect axi_ad9371_core/dac_enable_q0 util_ad9371_tx_upack/dac_enable_1
ad_connect axi_ad9371_core/dac_data_q0 util_ad9371_tx_upack/dac_data_1
ad_connect axi_ad9371_core/dac_valid_i1 util_ad9371_tx_upack/dac_valid_2
ad_connect axi_ad9371_core/dac_enable_i1 util_ad9371_tx_upack/dac_enable_2
ad_connect axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
ad_connect axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
ad_connect axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
ad_connect axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen
2017-08-22 12:35:14 +00:00
ad_connect axi_ad9371_tx_jesd_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-17 07:05:52 +00:00
ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 13:50:12 +00:00
ad_connect sys_dma_clk axi_ad9371_dacfifo/dma_clk
ad_connect sys_dma_clk axi_ad9371_tx_dma/m_axis_aclk
dacfifo- bypass port name change
2017-02-27 20:57:53 +00:00
ad_connect axi_ad9371_dacfifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
ad_connect axi_ad9371_dacfifo/dma_data axi_ad9371_tx_dma/m_axis_data
ad_connect axi_ad9371_dacfifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-17 07:05:52 +00:00
ad_connect axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
adrv9371x: Connect bypass and data underflow
2016-05-20 09:45:33 +00:00
ad_connect axi_ad9371_dacfifo/dac_dunf axi_ad9371_core/dac_dunf
dacfifo- bypass port name change
2017-02-27 20:57:53 +00:00
ad_connect axi_ad9371_dacfifo/bypass dac_fifo_bypass
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
adrv9371x: Connect bypass and data underflow
2016-05-20 09:45:33 +00:00
adrv9371x- added
2016-05-20 15:46:25 +00:00
# connections (adc)
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_connect axi_ad9371_rx_jesd/rx_sof axi_ad9371_core/adc_rx_sof
ad_connect axi_ad9371_rx_jesd/rx_data_tdata axi_ad9371_core/adc_rx_data
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
ad_connect axi_ad9371_rx_jesd_rstgen/peripheral_reset util_ad9371_rx_cpack/adc_rst
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_connect axi_ad9371_core/adc_enable_i0 util_ad9371_rx_cpack/adc_enable_0
ad_connect axi_ad9371_core/adc_valid_i0 util_ad9371_rx_cpack/adc_valid_0
ad_connect axi_ad9371_core/adc_data_i0 util_ad9371_rx_cpack/adc_data_0
ad_connect axi_ad9371_core/adc_enable_q0 util_ad9371_rx_cpack/adc_enable_1
ad_connect axi_ad9371_core/adc_valid_q0 util_ad9371_rx_cpack/adc_valid_1
ad_connect axi_ad9371_core/adc_data_q0 util_ad9371_rx_cpack/adc_data_1
ad_connect axi_ad9371_core/adc_enable_i1 util_ad9371_rx_cpack/adc_enable_2
ad_connect axi_ad9371_core/adc_valid_i1 util_ad9371_rx_cpack/adc_valid_2
ad_connect axi_ad9371_core/adc_data_i1 util_ad9371_rx_cpack/adc_data_2
ad_connect axi_ad9371_core/adc_enable_q1 util_ad9371_rx_cpack/adc_enable_3
ad_connect axi_ad9371_core/adc_valid_q1 util_ad9371_rx_cpack/adc_valid_3
ad_connect axi_ad9371_core/adc_data_q1 util_ad9371_rx_cpack/adc_data_3
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_connect util_ad9371_rx_cpack/adc_valid axi_ad9371_rx_dma/fifo_wr_en
ad_connect util_ad9371_rx_cpack/adc_sync axi_ad9371_rx_dma/fifo_wr_sync
ad_connect util_ad9371_rx_cpack/adc_data axi_ad9371_rx_dma/fifo_wr_din
ad_connect axi_ad9371_rx_dma/fifo_wr_overflow axi_ad9371_core/adc_dovf
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
# connections (adc-os)
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_connect axi_ad9371_rx_os_jesd/rx_sof axi_ad9371_core/adc_rx_os_sof
ad_connect axi_ad9371_rx_os_jesd/rx_data_tdata axi_ad9371_core/adc_rx_os_data
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
ad_connect axi_ad9371_rx_os_jesd_rstgen/peripheral_reset util_ad9371_rx_os_cpack/adc_rst
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_connect axi_ad9371_core/adc_os_enable_i0 util_ad9371_rx_os_cpack/adc_enable_0
ad_connect axi_ad9371_core/adc_os_valid_i0 util_ad9371_rx_os_cpack/adc_valid_0
ad_connect axi_ad9371_core/adc_os_data_i0 util_ad9371_rx_os_cpack/adc_data_0
ad_connect axi_ad9371_core/adc_os_enable_q0 util_ad9371_rx_os_cpack/adc_enable_1
ad_connect axi_ad9371_core/adc_os_valid_q0 util_ad9371_rx_os_cpack/adc_valid_1
ad_connect axi_ad9371_core/adc_os_data_q0 util_ad9371_rx_os_cpack/adc_data_1
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_connect util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
ad_connect util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
ad_connect util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
ad_connect axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_connect sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-17 07:05:52 +00:00
adrv9371x- added
2016-05-20 15:46:25 +00:00
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 axi_ad9371_core
adrv9371x: Change the axi_adxcvr cores addresses Because the S_AXI interface of the axi_adxcvr core was infered using the process adi_ip_properties, the interface address range has changed from 4k to 64k. As a result, all the addresses of the axi_adxcvr cores were changed and realigned.
2017-01-19 13:23:03 +00:00
ad_cpu_interconnect 0x44A80000 axi_ad9371_tx_xcvr
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
adrv9371x: Change the axi_adxcvr cores addresses Because the S_AXI interface of the axi_adxcvr core was infered using the process adi_ip_properties, the interface address range has changed from 4k to 64k. As a result, all the addresses of the axi_adxcvr cores were changed and realigned.
2017-01-19 13:23:03 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad9371_rx_xcvr
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad9371_rx_jesd
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
adrv9371x: Separate ps7 assignaments from common Move the assignaments/connections for ps7 from common/adrv9371_bd to zc706/system_bd
2017-08-18 13:21:34 +00:00
ad_cpu_interconnect 0x44A50000 axi_ad9371_rx_os_xcvr
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_cpu_interconnect 0x43C20000 axi_ad9371_rx_os_clkgen
adrv9371: Convert to ADI JESD204 core Convert the ADRV9371 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-14 09:50:48 +00:00
ad_cpu_interconnect 0x44AB0000 axi_ad9371_rx_os_jesd
adrv9371x- added
2016-05-20 15:46:25 +00:00
ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma
adrv9371x: Move GTs AXI interface to HP3 If the VDMA and the GTs AXI are connected to the same HP port, the HDMI won't work on full resolution (1080p). Care should be taken, this can affect the receive and observation paths (both are connected to HP2).
2016-05-19 14:19:57 +00:00
# gt uses hp3, and 100MHz clock for both DRP and AXI4
adrv9371x- added
2016-05-20 15:46:25 +00:00
adrv9371x: Move GTs AXI interface to HP3 If the VDMA and the GTs AXI are connected to the same HP port, the HDMI won't work on full resolution (1080p). Care should be taken, this can affect the receive and observation paths (both are connected to HP2).
2016-05-19 14:19:57 +00:00
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
adrv9371x - xcvr updates
2016-09-29 15:49:49 +00:00
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_xcvr/m_axi
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_os_xcvr/m_axi
adrv9371x- added
2016-05-20 15:46:25 +00:00
# interconnect (mem/dac)
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_dma_clk axi_ad9371_tx_dma/m_src_axi
ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_dma/m_dest_axi
ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi
# interrupts
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-8 mb-8 axi_ad9371_rx_os_jesd/irq
ad_cpu_interrupt ps-9 mb-7 axi_ad9371_tx_jesd/irq
ad_cpu_interrupt ps-10 mb-15 axi_ad9371_rx_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9371_rx_os_dma/irq
ad_cpu_interrupt ps-12 mb-13- axi_ad9371_tx_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9371_rx_dma/irq