2014-03-06 16:16:02 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module dmac_2d_transfer (
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2016-10-01 15:13:42 +00:00
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input req_aclk,
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input req_aresetn,
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2014-03-06 16:16:02 +00:00
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2016-10-01 15:13:42 +00:00
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input req_valid,
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output reg req_ready,
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2014-03-06 16:16:02 +00:00
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2016-10-01 15:13:42 +00:00
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input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
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input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
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input [DMA_LENGTH_WIDTH-1:0] req_x_length,
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input [DMA_LENGTH_WIDTH-1:0] req_y_length,
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input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
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input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
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input req_sync_transfer_start,
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output reg req_eot,
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output reg out_req_valid,
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input out_req_ready,
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output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
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output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
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output [DMA_LENGTH_WIDTH-1:0] out_req_length,
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output reg out_req_sync_transfer_start,
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input out_eot
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2014-03-06 16:16:02 +00:00
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);
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2015-08-19 11:11:47 +00:00
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parameter DMA_LENGTH_WIDTH = 24;
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parameter BYTES_PER_BEAT_WIDTH_SRC = 3;
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parameter BYTES_PER_BEAT_WIDTH_DEST = 3;
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2014-03-06 16:16:02 +00:00
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2015-08-19 11:11:47 +00:00
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reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address;
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reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address;
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reg [DMA_LENGTH_WIDTH-1:0] x_length;
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reg [DMA_LENGTH_WIDTH-1:0] y_length;
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reg [DMA_LENGTH_WIDTH-1:0] dest_stride;
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reg [DMA_LENGTH_WIDTH-1:0] src_stride;
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2014-03-06 16:16:02 +00:00
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reg [1:0] req_id;
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reg [1:0] eot_id;
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reg [3:0] last_req;
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assign out_req_dest_address = dest_address;
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assign out_req_src_address = src_address;
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assign out_req_length = x_length;
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always @(posedge req_aclk)
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begin
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2016-10-01 15:13:42 +00:00
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if (req_aresetn == 1'b0) begin
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req_id <= 2'b0;
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eot_id <= 2'b0;
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req_eot <= 1'b0;
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end else begin
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if (out_req_valid && out_req_ready) begin
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req_id <= req_id + 1'b1;
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last_req[req_id] <= y_length == 0;
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end
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req_eot <= 1'b0;
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if (out_eot) begin
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eot_id <= eot_id + 1'b1;
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req_eot <= last_req[eot_id];
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end
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end
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2014-03-06 16:16:02 +00:00
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end
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always @(posedge req_aclk)
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begin
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2016-10-01 15:13:42 +00:00
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if (req_aresetn == 1'b0) begin
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dest_address <= 'h00;
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src_address <= 'h00;
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x_length <= 'h00;
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y_length <= 'h00;
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dest_stride <= 'h00;
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src_stride <= 'h00;
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req_ready <= 1'b1;
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out_req_valid <= 1'b0;
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out_req_sync_transfer_start <= 1'b0;
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end else begin
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if (req_ready) begin
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if (req_valid) begin
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dest_address <= req_dest_address;
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src_address <= req_src_address;
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x_length <= req_x_length;
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y_length <= req_y_length;
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dest_stride <= req_dest_stride;
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src_stride <= req_src_stride;
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out_req_sync_transfer_start <= req_sync_transfer_start;
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req_ready <= 1'b0;
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out_req_valid <= 1'b1;
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end
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end else begin
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if (out_req_valid && out_req_ready) begin
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dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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y_length <= y_length - 1'b1;
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out_req_sync_transfer_start <= 1'b0;
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if (y_length == 0) begin
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out_req_valid <= 1'b0;
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req_ready <= 1'b1;
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end
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end
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end
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end
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2014-03-06 16:16:02 +00:00
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end
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endmodule
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