2015-05-11 09:09:09 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_tdd_control(
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// clock and reset
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clk,
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rst,
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// TDD timming signals
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2015-05-21 10:39:48 +00:00
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tdd_enable,
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2015-05-11 09:09:09 +00:00
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tdd_secondary,
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2015-05-21 10:39:48 +00:00
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tdd_txnrx_only_en,
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tdd_txnrx_only,
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tdd_burst_count,
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2015-05-11 09:09:09 +00:00
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tdd_counter_init,
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tdd_frame_length,
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tdd_vco_rx_on_1,
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tdd_vco_rx_off_1,
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tdd_vco_tx_on_1,
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tdd_vco_tx_off_1,
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tdd_rx_on_1,
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tdd_rx_off_1,
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tdd_tx_on_1,
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tdd_tx_off_1,
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tdd_tx_dp_on_1,
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tdd_tx_dp_off_1,
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tdd_vco_rx_on_2,
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tdd_vco_rx_off_2,
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tdd_vco_tx_on_2,
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tdd_vco_tx_off_2,
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tdd_rx_on_2,
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tdd_rx_off_2,
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tdd_tx_on_2,
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tdd_tx_off_2,
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tdd_tx_dp_on_2,
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tdd_tx_dp_off_2,
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// TDD control signals
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tdd_tx_dp_en,
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tdd_rx_vco_en,
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tdd_tx_vco_en,
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tdd_rx_rf_en,
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tdd_tx_rf_en,
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tdd_counter_status);
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// parameters
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localparam ON = 1;
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localparam OFF = 0;
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// input/output signals
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input clk;
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input rst;
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2015-05-21 10:39:48 +00:00
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input tdd_enable;
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2015-05-11 09:09:09 +00:00
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input tdd_secondary;
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2015-05-21 10:39:48 +00:00
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input tdd_txnrx_only_en;
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input tdd_txnrx_only;
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input [ 7:0] tdd_burst_count;
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input [23:0] tdd_counter_init;
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input [23:0] tdd_frame_length;
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input [23:0] tdd_vco_rx_on_1;
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input [23:0] tdd_vco_rx_off_1;
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input [23:0] tdd_vco_tx_on_1;
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input [23:0] tdd_vco_tx_off_1;
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input [23:0] tdd_rx_on_1;
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input [23:0] tdd_rx_off_1;
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input [23:0] tdd_tx_on_1;
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input [23:0] tdd_tx_off_1;
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input [23:0] tdd_tx_dp_on_1;
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input [23:0] tdd_tx_dp_off_1;
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input [23:0] tdd_vco_rx_on_2;
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input [23:0] tdd_vco_rx_off_2;
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input [23:0] tdd_vco_tx_on_2;
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input [23:0] tdd_vco_tx_off_2;
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input [23:0] tdd_rx_on_2;
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input [23:0] tdd_rx_off_2;
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input [23:0] tdd_tx_on_2;
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input [23:0] tdd_tx_off_2;
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input [23:0] tdd_tx_dp_on_2;
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input [23:0] tdd_tx_dp_off_2;
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2015-05-11 09:09:09 +00:00
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output tdd_tx_dp_en; // initiate vco tx2rx switch
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output tdd_rx_vco_en; // initiate vco rx2tx switch
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output tdd_tx_vco_en; // power up RF Rx
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output tdd_rx_rf_en; // power up RF Tx
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output tdd_tx_rf_en; // enable Tx datapath
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output [23:0] tdd_counter_status;
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// tdd control related
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reg tdd_tx_dp_en = 1'b0;
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reg tdd_rx_vco_en = 1'b0;
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reg tdd_tx_vco_en = 1'b0;
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reg tdd_rx_rf_en = 1'b0;
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reg tdd_tx_rf_en = 1'b0;
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// tdd counter related
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2015-05-21 10:39:48 +00:00
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reg [23:0] tdd_counter = 24'h0;
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2015-05-11 09:09:09 +00:00
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reg [ 5:0] tdd_burst_counter = 6'h0;
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reg tdd_counter_state = OFF;
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2015-05-13 11:03:01 +00:00
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reg counter_at_tdd_vco_rx_on_1 = 1'b0;
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reg counter_at_tdd_vco_rx_off_1 = 1'b0;
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reg counter_at_tdd_vco_tx_on_1 = 1'b0;
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reg counter_at_tdd_vco_tx_off_1 = 1'b0;
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reg counter_at_tdd_rx_on_1 = 1'b0;
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reg counter_at_tdd_rx_off_1 = 1'b0;
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reg counter_at_tdd_tx_on_1 = 1'b0;
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reg counter_at_tdd_tx_off_1 = 1'b0;
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reg counter_at_tdd_tx_dp_on_1 = 1'b0;
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reg counter_at_tdd_tx_dp_off_1 = 1'b0;
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reg counter_at_tdd_vco_rx_on_2 = 1'b0;
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reg counter_at_tdd_vco_rx_off_2 = 1'b0;
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reg counter_at_tdd_vco_tx_on_2 = 1'b0;
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reg counter_at_tdd_vco_tx_off_2 = 1'b0;
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reg counter_at_tdd_rx_on_2 = 1'b0;
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reg counter_at_tdd_rx_off_2 = 1'b0;
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reg counter_at_tdd_tx_on_2 = 1'b0;
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reg counter_at_tdd_tx_off_2 = 1'b0;
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reg counter_at_tdd_tx_dp_on_2 = 1'b0;
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reg counter_at_tdd_tx_dp_off_2 = 1'b0;
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2015-05-21 10:39:48 +00:00
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reg tdd_enable_d = 1'h0;
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2015-05-13 11:03:01 +00:00
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2015-05-21 10:39:48 +00:00
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// internal signals
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2015-05-11 09:09:09 +00:00
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2015-05-21 10:39:48 +00:00
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wire [23:0] tdd_tx_dp_on_1_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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2015-05-11 09:09:09 +00:00
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2015-05-13 11:03:01 +00:00
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assign tdd_counter_status = tdd_counter;
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2015-05-11 09:09:09 +00:00
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// ***************************************************************************
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// tdd counter (state machine)
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// ***************************************************************************
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always @(posedge clk) begin
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// sync reset
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if (rst == 1'b1) begin
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tdd_counter <= 24'h0;
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tdd_counter_state <= OFF;
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end else begin
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// counter reset
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2015-05-21 10:39:48 +00:00
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if (tdd_enable == 1'b0) begin
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2015-05-11 09:09:09 +00:00
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tdd_counter_state <= OFF;
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2015-05-21 10:39:48 +00:00
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tdd_enable_d <= tdd_enable;
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2015-05-11 09:09:09 +00:00
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end else
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2015-05-21 10:39:48 +00:00
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// start counter on the positive edge of the tdd_enable
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if ((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
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2015-05-13 11:03:01 +00:00
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tdd_counter <= tdd_counter_init;
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tdd_burst_counter <= tdd_burst_count;
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2015-05-11 09:09:09 +00:00
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tdd_counter_state <= ON;
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end else
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// free running counter
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if (tdd_counter_state == ON) begin
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2015-05-13 11:03:01 +00:00
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if (tdd_counter == tdd_frame_length) begin
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2015-05-11 09:09:09 +00:00
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tdd_counter <= 22'h0;
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2015-05-21 10:39:48 +00:00
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if ( tdd_burst_counter > 1) begin // inside a burst
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tdd_burst_counter <= tdd_burst_counter - 1;
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tdd_counter_state <= ON;
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end
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else
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if ( tdd_burst_counter == 1) begin // end of burst
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tdd_burst_counter <= 6'h0;
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tdd_counter_state <= OFF;
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2015-05-13 11:03:01 +00:00
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end
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else begin // contiuous mode
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2015-05-11 09:09:09 +00:00
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tdd_burst_counter <= 6'h0;
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2015-05-13 11:03:01 +00:00
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tdd_counter_state <= ON;
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2015-05-11 09:09:09 +00:00
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end
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2015-05-13 11:03:01 +00:00
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end
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else begin
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2015-05-11 09:09:09 +00:00
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tdd_counter <= tdd_counter + 1;
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end
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end
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end
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end
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// ***************************************************************************
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// generate control signals
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// ***************************************************************************
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// start/stop rx vco
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2015-05-13 11:03:01 +00:00
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always @(posedge clk) begin
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if(tdd_counter == tdd_vco_rx_on_1) begin
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counter_at_tdd_vco_rx_on_1 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_rx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2)) begin
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counter_at_tdd_vco_rx_on_2 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_rx_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(tdd_counter == tdd_vco_rx_off_1) begin
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counter_at_tdd_vco_rx_off_1 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_rx_off_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2)) begin
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counter_at_tdd_vco_rx_off_2 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_rx_off_2 <= 1'b0;
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end
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end
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// start/stop tx vco
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always @(posedge clk) begin
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if(tdd_counter == tdd_vco_tx_on_1) begin
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counter_at_tdd_vco_tx_on_1 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_tx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2)) begin
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counter_at_tdd_vco_tx_on_2 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_tx_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(tdd_counter == tdd_vco_tx_off_1) begin
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counter_at_tdd_vco_tx_off_1 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_tx_off_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2)) begin
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counter_at_tdd_vco_tx_off_2 <= 1'b1;
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end
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else begin
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counter_at_tdd_vco_tx_off_2 <= 1'b0;
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end
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end
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// start/stop rx rf path
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always @(posedge clk) begin
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if(tdd_counter == tdd_rx_on_1) begin
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counter_at_tdd_rx_on_1 <= 1'b1;
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end
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else begin
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counter_at_tdd_rx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2)) begin
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counter_at_tdd_rx_on_2 <= 1'b1;
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end
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else begin
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counter_at_tdd_rx_on_2 <= 1'b0;
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end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter == tdd_rx_off_1) begin
|
|
|
|
counter_at_tdd_rx_off_1 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_rx_off_1 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2)) begin
|
|
|
|
counter_at_tdd_rx_off_2 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_rx_off_2 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
// start/stop tx rf path
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter == tdd_tx_on_1) begin
|
|
|
|
counter_at_tdd_tx_on_1 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_on_1 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2)) begin
|
|
|
|
counter_at_tdd_tx_on_2 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_on_2 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter == tdd_tx_off_1) begin
|
|
|
|
counter_at_tdd_tx_off_1 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_off_1 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2)) begin
|
|
|
|
counter_at_tdd_tx_off_2 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_off_2 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
// start/stop tx data path
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter == tdd_tx_dp_on_1_s) begin
|
|
|
|
counter_at_tdd_tx_dp_on_1 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_dp_on_1 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
|
|
|
|
counter_at_tdd_tx_dp_on_2 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_dp_on_2 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter == tdd_tx_dp_off_1_s) begin
|
|
|
|
counter_at_tdd_tx_dp_off_1 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_dp_off_1 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
|
|
|
|
counter_at_tdd_tx_dp_off_2 <= 1'b1;
|
|
|
|
end
|
|
|
|
else begin
|
|
|
|
counter_at_tdd_tx_dp_off_2 <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
// internal datapath delay compensation
|
|
|
|
|
|
|
|
ad_addsub #(
|
2015-05-21 10:39:48 +00:00
|
|
|
.A_WIDTH(24),
|
2015-05-13 11:03:01 +00:00
|
|
|
.CONST_VALUE(11),
|
|
|
|
.ADD_SUB(1)
|
|
|
|
) i_tx_dp_on_1_comp (
|
|
|
|
.clk(clk),
|
|
|
|
.A(tdd_tx_dp_on_1),
|
|
|
|
.overflow(tdd_frame_length),
|
|
|
|
.out(tdd_tx_dp_on_1_s),
|
|
|
|
.CE(1)
|
|
|
|
);
|
|
|
|
|
|
|
|
ad_addsub #(
|
2015-05-21 10:39:48 +00:00
|
|
|
.A_WIDTH(24),
|
2015-05-13 11:03:01 +00:00
|
|
|
.CONST_VALUE(11),
|
|
|
|
.ADD_SUB(1)
|
|
|
|
) i_tx_dp_on_2_comp (
|
|
|
|
.clk(clk),
|
|
|
|
.A(tdd_tx_dp_on_2),
|
|
|
|
.overflow(tdd_frame_length),
|
|
|
|
.out(tdd_tx_dp_on_2_s),
|
|
|
|
.CE(1)
|
|
|
|
);
|
|
|
|
|
|
|
|
ad_addsub #(
|
2015-05-21 10:39:48 +00:00
|
|
|
.A_WIDTH(24),
|
2015-05-13 11:03:01 +00:00
|
|
|
.CONST_VALUE(11),
|
|
|
|
.ADD_SUB(1)
|
|
|
|
) i_tx_dp_off_1_comp (
|
|
|
|
.clk(clk),
|
|
|
|
.A(tdd_tx_dp_off_1),
|
|
|
|
.overflow(tdd_frame_length),
|
|
|
|
.out(tdd_tx_dp_off_1_s),
|
|
|
|
.CE(1)
|
|
|
|
);
|
|
|
|
|
|
|
|
ad_addsub #(
|
2015-05-21 10:39:48 +00:00
|
|
|
.A_WIDTH(24),
|
2015-05-13 11:03:01 +00:00
|
|
|
.CONST_VALUE(11),
|
|
|
|
.ADD_SUB(1)
|
|
|
|
) i_tx_dp_off_2_comp (
|
|
|
|
.clk(clk),
|
|
|
|
.A(tdd_tx_dp_off_2),
|
|
|
|
.overflow(tdd_frame_length),
|
|
|
|
.out(tdd_tx_dp_off_2_s),
|
|
|
|
.CE(1)
|
|
|
|
);
|
|
|
|
|
|
|
|
// output logic
|
|
|
|
|
2015-05-11 09:09:09 +00:00
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter_state == ON) begin
|
2015-05-21 10:39:48 +00:00
|
|
|
if (tdd_txnrx_only_en) begin
|
|
|
|
tdd_rx_vco_en <= ~tdd_txnrx_only;
|
|
|
|
end
|
|
|
|
else if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_rx_vco_en <= 1'b1;
|
2015-05-13 11:03:01 +00:00
|
|
|
end
|
|
|
|
else if (counter_at_tdd_vco_rx_off_1 || counter_at_tdd_vco_rx_off_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_rx_vco_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end else begin
|
|
|
|
tdd_rx_vco_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter_state == ON) begin
|
2015-05-21 10:39:48 +00:00
|
|
|
if (tdd_txnrx_only_en) begin
|
|
|
|
tdd_tx_vco_en <= tdd_txnrx_only;
|
|
|
|
end
|
|
|
|
else if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_tx_vco_en <= 1'b1;
|
2015-05-13 11:03:01 +00:00
|
|
|
end
|
|
|
|
else if (counter_at_tdd_vco_tx_off_1 || counter_at_tdd_vco_tx_off_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_tx_vco_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end else begin
|
|
|
|
tdd_tx_vco_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter_state == ON) begin
|
2015-05-21 10:39:48 +00:00
|
|
|
if (tdd_txnrx_only_en) begin
|
|
|
|
tdd_rx_rf_en <= ~tdd_txnrx_only;
|
|
|
|
end
|
|
|
|
else if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_rx_rf_en <= 1'b1;
|
2015-05-13 11:03:01 +00:00
|
|
|
end
|
|
|
|
else if (counter_at_tdd_rx_off_1 || counter_at_tdd_rx_off_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_rx_rf_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end else begin
|
|
|
|
tdd_rx_rf_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter_state == ON) begin
|
2015-05-21 10:39:48 +00:00
|
|
|
if (tdd_txnrx_only_en) begin
|
|
|
|
tdd_tx_rf_en <= tdd_txnrx_only;
|
|
|
|
end
|
|
|
|
else if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_tx_rf_en <= 1'b1;
|
2015-05-13 11:03:01 +00:00
|
|
|
end
|
|
|
|
else if (counter_at_tdd_tx_off_1 || counter_at_tdd_tx_off_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_tx_rf_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end else begin
|
|
|
|
tdd_tx_rf_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
if(tdd_counter_state == ON) begin
|
2015-05-21 10:39:48 +00:00
|
|
|
if (tdd_txnrx_only_en) begin
|
|
|
|
tdd_tx_dp_en <= tdd_txnrx_only;
|
|
|
|
end
|
|
|
|
else if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_tx_dp_en <= 1'b1;
|
2015-05-13 11:03:01 +00:00
|
|
|
end
|
|
|
|
else if (counter_at_tdd_tx_dp_off_1 || counter_at_tdd_tx_dp_off_2) begin
|
2015-05-11 09:09:09 +00:00
|
|
|
tdd_tx_dp_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end else begin
|
|
|
|
tdd_tx_dp_en <= 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|