pluto_hdl_adi/library/util_cic/cic_comb.v

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module cic_comb #(
  parameter DATA_WIDTH = 32,
  parameter SEQ = 1
) (
  input clk,
  input ce,
  input [DATA_WIDTH-1:0] data_in,
  output [DATA_WIDTH-1:0] data_out
);

reg [SEQ-1:0] storage[0:DATA_WIDTH-1];
reg [DATA_WIDTH-1:0] state = 'h00;

reg [2:0] counter = 'h00;
reg active = 1'b0;

integer x;

initial begin
  for (x = 0; x < DATA_WIDTH; x = x + 1) begin
    storage[x] = 'h00;
  end
end

generate if (SEQ != 1) begin

always @(posedge clk) begin
  if (ce == 1'b1) begin
    counter <= SEQ-1;
    active <= 1'b1;
  end else if (active == 1'b1) begin
    counter <= counter - 1'b1;
    if (counter == 'h1) begin
      active <= 1'b0;
    end
  end
end

end
endgenerate

reg [DATA_WIDTH-1:0] data_in_seq;
wire [DATA_WIDTH-1:0] storage_out;

always @(*) begin
  if (ce == 1'b1) begin
    data_in_seq <= data_in;
  end else begin
    data_in_seq <= SEQ != 1 ? state : 'h00;
  end
end

always @(posedge clk) begin
  if (ce == 1'b1 || active == 1'b1) begin
    state <= data_in_seq - storage_out;
  end
end

generate
  genvar i;

  for (i = 0; i < DATA_WIDTH; i = i + 1) begin: shift_r
    always @(posedge clk) begin
      if (ce == 1'b1 || active == 1'b1) begin
        if (SEQ > 1) begin
          storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]};
        end else begin
          storage[i] <= data_in_seq[i];
        end
      end
    end

    assign storage_out[i] = storage[i][SEQ-1];
  end
endgenerate

assign data_out = state;

endmodule