2016-08-16 12:50:46 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
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create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
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derive_pll_clocks
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derive_clock_uncertainty
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2017-06-05 19:24:35 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
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set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
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2016-08-16 12:50:46 +00:00
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