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pluto_hdl_adi/projects/adrv9371x/a10soc/system_constr.sdc

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adrv9371x- added
2016-05-20 15:46:25 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
a10soc- updates-1
2016-05-20 20:14:57 +00:00
create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
adrv9371x- added
2016-05-20 15:46:25 +00:00
derive_pll_clocks
derive_clock_uncertainty
adrv9371x- need to investigate merge with avalon
2016-06-02 20:22:40 +00:00
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_clk}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_os_clk}]
set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|tx_dac_clk}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_clk}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|adrv9371x|xcvr_pll|rx_adc_os_clk}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]