183 lines
6.5 KiB
Coq
183 lines
6.5 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_top(
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clk,
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// gpio
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gpio_input,
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gpio_output,
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// TX side
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dma_dac_drd,
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dma_dac_dunf,
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dma_dac_ddata,
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core_dac_drd,
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core_dac_dunf,
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core_dac_ddata,
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// RX side
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core_adc_dwr,
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core_adc_dsync,
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core_adc_ddata,
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core_adc_ovf,
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dma_adc_dwr,
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dma_adc_dsync,
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dma_adc_ddata,
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dma_adc_ovf
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);
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localparam ENABELED = 1;
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localparam DATA_WIDTH = 32;
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parameter NUM_CHANNEL = 2;
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parameter ADC_EN = 1;
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parameter DAC_EN = 1;
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localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
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input clk;
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input [31:0] gpio_input;
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output [31:0] gpio_output;
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output dma_dac_drd;
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input dma_dac_dunf;
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input [(DBUS_WIDTH - 1):0] dma_dac_ddata;
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input core_dac_drd;
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output core_dac_dunf;
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output [(DBUS_WIDTH - 1):0] core_dac_ddata;
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input core_adc_dwr;
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input core_adc_dsync;
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input [(DBUS_WIDTH - 1):0] core_adc_ddata;
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output core_adc_ovf;
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output dma_adc_dwr;
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output dma_adc_dsync;
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output [(DBUS_WIDTH - 1):0] dma_adc_ddata;
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input dma_adc_ovf;
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wire [31:0] adc_status_s[(NUM_CHANNEL - 1):0];
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wire [31:0] dac_status_s[(NUM_CHANNEL - 1):0];
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genvar l_inst;
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generate
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for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
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if(ADC_EN == ENABELED) begin
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if(l_inst == 0) begin
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prcfg_adc #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_adc_1 (
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.clk(clk),
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.control(gpio_input),
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.status(adc_status_s[l_inst]),
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.src_adc_dwr(core_adc_dwr),
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.src_adc_dsync(core_adc_dsync),
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.src_adc_ddata(core_adc_ddata[(DATA_WIDTH - 1):0]),
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.src_adc_dovf(core_adc_ovf),
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.dst_adc_dwr(dma_adc_dwr),
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.dst_adc_dsync(dma_adc_dsync),
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.dst_adc_ddata(dma_adc_ddata[(DATA_WIDTH - 1):0]),
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.dst_adc_dovf(dma_adc_ovf)
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);
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end else begin
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prcfg_adc #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_adc_1 (
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.clk(clk),
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.control(gpio_input),
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.status(adc_status_s[l_inst]),
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.src_adc_dwr(core_adc_dwr),
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.src_adc_dsync(core_adc_dsync),
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.src_adc_ddata(core_adc_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
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.src_adc_dovf(),
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.dst_adc_dwr(),
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.dst_adc_dsync(),
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.dst_adc_ddata(dma_adc_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
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.dst_adc_dovf(dma_adc_ovf)
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);
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end
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end
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if(DAC_EN == ENABELED) begin
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if(l_inst == 0) begin
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prcfg_dac #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_dac_1 (
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.clk(clk),
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.control(gpio_input),
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.status(dac_status_s[l_inst]),
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.src_dac_drd(dma_dac_drd),
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.src_dac_ddata(dma_dac_ddata[(DATA_WIDTH - 1):0]),
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.src_dac_dunf(dma_dac_dunf),
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.dst_dac_drd(core_dac_drd),
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.dst_dac_ddata(core_dac_ddata[(DATA_WIDTH - 1):0]),
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.dst_dac_dunf(core_dac_dunf)
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);
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end else begin
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prcfg_dac #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_dac_1 (
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.clk(clk),
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.control(gpio_input),
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.status(dac_status_s[l_inst]),
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.src_dac_drd(),
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.src_dac_ddata(dma_dac_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
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.src_dac_dunf(dma_dac_dunf),
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.dst_dac_drd(core_dac_drd),
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.dst_dac_ddata(core_dac_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
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.dst_dac_dunf()
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);
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end
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end
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assign gpio_output = gpio_output | adc_status_s[l_inst] | dac_status_s[l_inst];
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end
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endgenerate
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endmodule
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