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pluto_hdl_adi/projects/dac_fmc_ebz/zc706/system_bd.tcl

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dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
# ***************************************************************************
# ***************************************************************************
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# In this HDL repository, there are many different and unique modules, consisting
# of various HDL (Verilog or VHDL) components. The individual modules are
# developed independently, and may be accompanied by separate and unique license
# terms.
#
# The user should read each of these license terms, and understand the
# freedoms and responsibilities that he or she has by using this source/core.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE.
#
# Redistribution and use of source or resulting binaries, with or without modification
# of this file, are permitted under one of the following two license terms:
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory
# of this repository (LICENSE_GPL2), and also online at:
# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
#
# OR
#
# 2. An ADI specific BSD license, which can be found in the top level directory
# of this repository (LICENSE_ADIBSD), and also on-line at:
# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
# This will allow to generate bit files and not release the source code,
# as long as it attaches to an ADI device.
#
# ***************************************************************************
# ***************************************************************************
set dac_fifo_address_width 14
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source ../common/dac_fmc_ebz_bd.tcl
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
ad_ip_parameter dac_jesd204_link/tx CONFIG.SYSREF_IOB false