zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc

36 lines
2.0 KiB
Plaintext
Raw Normal View History

axi_dacfifo: Fix constraints
2017-02-21 12:45:18 +00:00
set_property ASYNC_REG TRUE \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
[get_cells -hier *dma_mem_*_m*] \
[get_cells -hier *axi_xfer_*_m*] \
[get_cells -hier *axi_mem_*_m*] \
[get_cells -hier *axi_dma_*_m*] \
[get_cells -hier *dac_mem_*_m*] \
[get_cells -hier *dac_xfer_*_m*] \
[get_cells -hier *dac_last_*_m*] \
[get_cells -hier *dac_bypass_m*]
axi_dacfifo: Update the constraints
2016-05-24 15:09:27 +00:00
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1_reg && IS_SEQUENTIAL}]
axi_dacfifo: Update constraints
2017-08-18 09:39:22 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1_reg && IS_SEQUENTIAL}]
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
-to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 09:24:54 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
-to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_mem_laddr* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_mem_laddr* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *i_laddress_buffer*m_ram_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_mem_raddr_reg* && IS_SEQUENTIAL}]