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pluto_hdl_adi/library/xilinx/axi_dacfifo/Makefile

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axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
updated makefiles
2016-12-09 21:06:41 +00:00
M_DEPS += ../../common/ad_axis_inf_rx.v
hdlmake.pl - updates
2017-07-20 19:11:21 +00:00
M_DEPS += ../../common/ad_b2g.v
M_DEPS += ../../common/ad_g2b.v
updated makefiles
2016-12-09 21:06:41 +00:00
M_DEPS += ../../common/ad_mem_asym.v
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
M_DEPS += ../../common/ad_mem.v
axi_dacfifo: Fix Makefile
2017-04-24 08:46:29 +00:00
M_DEPS += ../../common/util_dacfifo_bypass.v
axi_dacfifo: Move IP to library/xilinx
2016-09-15 08:38:16 +00:00
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
updated makefiles
2016-12-09 21:06:41 +00:00
M_DEPS += axi_dacfifo.v
make: Update Make files
2016-06-29 11:49:16 +00:00
M_DEPS += axi_dacfifo_constr.xdc
updated makefiles
2016-12-09 21:06:41 +00:00
M_DEPS += axi_dacfifo_ip.tcl
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
M_DEPS += axi_dacfifo_rd.v
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
M_DEPS += axi_dacfifo_address_buffer.v
updated makefiles
2016-12-09 21:06:41 +00:00
M_DEPS += axi_dacfifo_wr.v
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
hdl make updates
2016-06-01 17:53:09 +00:00
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
M_FLIST += .Xil
hdlmake updates
2017-04-25 19:46:26 +00:00
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
.PHONY: all clean clean-all
all: axi_dacfifo.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_dacfifo.xpr: $(M_DEPS)
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 12:16:04 +00:00
-rm -rf $(M_FLIST)
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
$(M_VIVADO) axi_dacfifo_ip.tcl >> axi_dacfifo_ip.log 2>&1
####################################################################################
####################################################################################