2016-12-08 15:33:35 +00:00
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# usdrx1-xcvr
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2017-05-12 17:40:14 +00:00
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add_instance avl_usdrx1_xcvr avl_adxcvr
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2017-06-15 14:20:52 +00:00
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set_instance_parameter_value avl_usdrx1_xcvr {ID} {0}
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2016-12-08 15:33:35 +00:00
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set_instance_parameter_value avl_usdrx1_xcvr {TX_OR_RX_N} {0}
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2017-06-15 14:20:52 +00:00
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set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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2016-12-08 15:33:35 +00:00
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set_instance_parameter_value avl_usdrx1_xcvr {LANE_RATE} {3200.0}
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set_instance_parameter_value avl_usdrx1_xcvr {REFCLK_FREQUENCY} {80.0}
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set_instance_parameter_value avl_usdrx1_xcvr {NUM_OF_LANES} {8}
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set_instance_parameter_value avl_usdrx1_xcvr {NUM_OF_CONVS} {32}
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set_instance_parameter_value avl_usdrx1_xcvr {FRM_BCNT} {4}
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set_instance_parameter_value avl_usdrx1_xcvr {FRM_SCNT} {1}
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set_instance_parameter_value avl_usdrx1_xcvr {MF_FCNT} {32}
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set_instance_parameter_value avl_usdrx1_xcvr {HD} {0}
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add_connection sys_clk.clk avl_usdrx1_xcvr.sys_clk
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add_connection sys_clk.clk_reset avl_usdrx1_xcvr.sys_resetn
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add_interface rx_ref_clk clock sink
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set_interface_property rx_ref_clk EXPORT_OF avl_usdrx1_xcvr.ref_clk
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add_interface rx_data_0 conduit end
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set_interface_property rx_data_0 EXPORT_OF avl_usdrx1_xcvr.rx_data_0
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add_interface rx_data_1 conduit end
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set_interface_property rx_data_1 EXPORT_OF avl_usdrx1_xcvr.rx_data_1
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add_interface rx_data_2 conduit end
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set_interface_property rx_data_2 EXPORT_OF avl_usdrx1_xcvr.rx_data_2
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add_interface rx_data_3 conduit end
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set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_3
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add_interface rx_data_4 conduit end
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2016-12-08 21:05:07 +00:00
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set_interface_property rx_data_4 EXPORT_OF avl_usdrx1_xcvr.rx_data_4
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2016-12-08 15:33:35 +00:00
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add_interface rx_data_5 conduit end
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2016-12-08 21:05:07 +00:00
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set_interface_property rx_data_5 EXPORT_OF avl_usdrx1_xcvr.rx_data_5
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2016-12-08 15:33:35 +00:00
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add_interface rx_data_6 conduit end
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2016-12-08 21:05:07 +00:00
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set_interface_property rx_data_6 EXPORT_OF avl_usdrx1_xcvr.rx_data_6
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2016-12-08 15:33:35 +00:00
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add_interface rx_data_7 conduit end
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2016-12-08 21:05:07 +00:00
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set_interface_property rx_data_7 EXPORT_OF avl_usdrx1_xcvr.rx_data_7
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2016-12-08 15:33:35 +00:00
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add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF avl_usdrx1_xcvr.sysref
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF avl_usdrx1_xcvr.sync
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add_interface rx_ip_sof conduit end
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set_interface_property rx_ip_sof EXPORT_OF avl_usdrx1_xcvr.ip_sof
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add_interface rx_ip_data avalon_streaming source
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set_interface_property rx_ip_data EXPORT_OF avl_usdrx1_xcvr.ip_data
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# usdrx1-xcvr
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2017-05-12 17:40:14 +00:00
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add_instance axi_usdrx1_xcvr axi_adxcvr
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2017-06-15 14:20:52 +00:00
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set_instance_parameter_value axi_usdrx1_xcvr {ID} {0}
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2016-12-08 15:33:35 +00:00
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set_instance_parameter_value axi_usdrx1_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value axi_usdrx1_xcvr {NUM_OF_LANES} {8}
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add_connection sys_clk.clk axi_usdrx1_xcvr.s_axi_clock
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add_connection sys_clk.clk_reset axi_usdrx1_xcvr.s_axi_reset
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add_connection axi_usdrx1_xcvr.if_up_rst avl_usdrx1_xcvr.rst
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add_connection avl_usdrx1_xcvr.ready axi_usdrx1_xcvr.ready
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add_connection axi_usdrx1_xcvr.core_pll_locked avl_usdrx1_xcvr.core_pll_locked
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# ad9671
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9671_core_0 axi_ad9671
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2016-12-08 21:05:07 +00:00
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set_instance_parameter_value axi_ad9671_core_0 {ID} {0}
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set_instance_parameter_value axi_ad9671_core_0 {QUAD_OR_DUAL_N} {0}
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2016-12-08 15:33:35 +00:00
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add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_0.if_rx_clk
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add_interface rx_ip_sof_0 conduit end
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set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9671_core_0.if_rx_sof
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add_interface rx_ip_data_0 avalon_streaming sink
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set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9671_core_0.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9671_core_0.s_axi_reset
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add_connection sys_clk.clk axi_ad9671_core_0.s_axi_clock
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2016-12-08 21:05:07 +00:00
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add_interface rx_core_ch_0 conduit end
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set_interface_property rx_core_ch_0 EXPORT_OF axi_ad9671_core_0.adc_ch
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add_interface rx_core_sync_0 conduit end
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set_interface_property rx_core_sync_0 EXPORT_OF axi_ad9671_core_0.if_sync
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add_interface rx_core_ovf_0 conduit end
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set_interface_property rx_core_ovf_0 EXPORT_OF axi_ad9671_core_0.if_adc_dovf
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add_interface rx_core_unf_0 conduit end
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set_interface_property rx_core_unf_0 EXPORT_OF axi_ad9671_core_0.if_adc_dunf
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2016-12-08 15:33:35 +00:00
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9671_core_1 axi_ad9671
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2016-12-08 21:05:07 +00:00
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set_instance_parameter_value axi_ad9671_core_1 {ID} {1}
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set_instance_parameter_value axi_ad9671_core_1 {QUAD_OR_DUAL_N} {0}
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2016-12-08 15:33:35 +00:00
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add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_1.if_rx_clk
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add_interface rx_ip_sof_1 conduit end
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set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9671_core_1.if_rx_sof
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add_interface rx_ip_data_1 avalon_streaming sink
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set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9671_core_1.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9671_core_1.s_axi_reset
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add_connection sys_clk.clk axi_ad9671_core_1.s_axi_clock
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2016-12-08 21:05:07 +00:00
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add_interface rx_core_ch_1 conduit end
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set_interface_property rx_core_ch_1 EXPORT_OF axi_ad9671_core_1.adc_ch
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add_interface rx_core_sync_1 conduit end
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set_interface_property rx_core_sync_1 EXPORT_OF axi_ad9671_core_1.if_sync
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add_interface rx_core_ovf_1 conduit end
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set_interface_property rx_core_ovf_1 EXPORT_OF axi_ad9671_core_1.if_adc_dovf
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add_interface rx_core_unf_1 conduit end
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set_interface_property rx_core_unf_1 EXPORT_OF axi_ad9671_core_1.if_adc_dunf
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2016-12-08 15:33:35 +00:00
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9671_core_2 axi_ad9671
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2016-12-08 21:05:07 +00:00
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set_instance_parameter_value axi_ad9671_core_2 {ID} {2}
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set_instance_parameter_value axi_ad9671_core_2 {QUAD_OR_DUAL_N} {0}
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2016-12-08 15:33:35 +00:00
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add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_2.if_rx_clk
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add_interface rx_ip_sof_2 conduit end
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set_interface_property rx_ip_sof_2 EXPORT_OF axi_ad9671_core_2.if_rx_sof
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add_interface rx_ip_data_2 avalon_streaming sink
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set_interface_property rx_ip_data_2 EXPORT_OF axi_ad9671_core_2.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9671_core_2.s_axi_reset
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add_connection sys_clk.clk axi_ad9671_core_2.s_axi_clock
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2016-12-08 21:05:07 +00:00
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add_interface rx_core_ch_2 conduit end
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set_interface_property rx_core_ch_2 EXPORT_OF axi_ad9671_core_2.adc_ch
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add_interface rx_core_sync_2 conduit end
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set_interface_property rx_core_sync_2 EXPORT_OF axi_ad9671_core_2.if_sync
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add_interface rx_core_ovf_2 conduit end
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set_interface_property rx_core_ovf_2 EXPORT_OF axi_ad9671_core_2.if_adc_dovf
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add_interface rx_core_unf_2 conduit end
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set_interface_property rx_core_unf_2 EXPORT_OF axi_ad9671_core_2.if_adc_dunf
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2016-12-08 15:33:35 +00:00
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9671_core_3 axi_ad9671
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2016-12-08 21:05:07 +00:00
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set_instance_parameter_value axi_ad9671_core_3 {ID} {3}
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set_instance_parameter_value axi_ad9671_core_3 {QUAD_OR_DUAL_N} {0}
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2016-12-08 15:33:35 +00:00
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add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_3.if_rx_clk
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add_interface rx_ip_sof_3 conduit end
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set_interface_property rx_ip_sof_3 EXPORT_OF axi_ad9671_core_3.if_rx_sof
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add_interface rx_ip_data_3 avalon_streaming sink
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set_interface_property rx_ip_data_3 EXPORT_OF axi_ad9671_core_3.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9671_core_3.s_axi_reset
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add_connection sys_clk.clk axi_ad9671_core_3.s_axi_clock
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2016-12-08 21:05:07 +00:00
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add_interface rx_core_ch_3 conduit end
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set_interface_property rx_core_ch_3 EXPORT_OF axi_ad9671_core_3.adc_ch
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add_interface rx_core_sync_3 conduit end
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set_interface_property rx_core_sync_3 EXPORT_OF axi_ad9671_core_3.if_sync
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add_interface rx_core_ovf_3 conduit end
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set_interface_property rx_core_ovf_3 EXPORT_OF axi_ad9671_core_3.if_adc_dovf
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add_interface rx_core_unf_3 conduit end
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set_interface_property rx_core_unf_3 EXPORT_OF axi_ad9671_core_3.if_adc_dunf
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2016-12-08 15:33:35 +00:00
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# usdrx1-fifo
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2017-05-12 17:40:14 +00:00
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add_instance usdrx1_adcfifo util_adcfifo
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2016-12-08 15:33:35 +00:00
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set_instance_parameter_value usdrx1_adcfifo {ADC_DATA_WIDTH} {512}
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set_instance_parameter_value usdrx1_adcfifo {DMA_DATA_WIDTH} {512}
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2016-12-08 21:05:07 +00:00
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set_instance_parameter_value usdrx1_adcfifo {DMA_ADDRESS_WIDTH} {10}
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2016-12-08 15:33:35 +00:00
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add_connection sys_clk.clk_reset usdrx1_adcfifo.if_adc_rst
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add_connection sys_dma_clk.clk_reset usdrx1_adcfifo.if_adc_rst
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add_connection avl_usdrx1_xcvr.core_clk usdrx1_adcfifo.if_adc_clk
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2016-12-08 21:05:07 +00:00
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add_interface rx_ch_wr conduit end
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set_interface_property rx_ch_wr EXPORT_OF usdrx1_adcfifo.if_adc_wr
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add_interface rx_ch_wdata conduit end
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set_interface_property rx_ch_wdata EXPORT_OF usdrx1_adcfifo.if_adc_wdata
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add_interface rx_ch_wovf conduit end
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set_interface_property rx_ch_wovf EXPORT_OF usdrx1_adcfifo.if_adc_wovf
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2016-12-08 15:33:35 +00:00
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add_connection sys_dma_clk.clk usdrx1_adcfifo.if_dma_clk
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# usdrx1-dma
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2017-05-12 17:40:14 +00:00
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add_instance axi_usdrx1_dma axi_dmac
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2017-06-15 14:20:52 +00:00
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set_instance_parameter_value axi_usdrx1_dma {ID} {0}
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set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_SRC} {1}
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set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_usdrx1_dma {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_usdrx1_dma {DMA_LENGTH_WIDTH} {24}
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2016-12-08 15:33:35 +00:00
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set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_SRC} {512}
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set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_DEST} {512}
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add_connection sys_dma_clk.clk axi_usdrx1_dma.if_s_axis_aclk
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add_connection usdrx1_adcfifo.if_dma_wr axi_usdrx1_dma.if_s_axis_valid
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add_connection usdrx1_adcfifo.if_dma_wdata axi_usdrx1_dma.if_s_axis_data
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add_connection usdrx1_adcfifo.if_dma_wready axi_usdrx1_dma.if_s_axis_ready
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add_connection usdrx1_adcfifo.if_dma_xfer_req axi_usdrx1_dma.if_s_axis_xfer_req
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add_connection sys_clk.clk_reset axi_usdrx1_dma.s_axi_reset
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add_connection sys_clk.clk axi_usdrx1_dma.s_axi_clock
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add_connection sys_dma_clk.clk_reset axi_usdrx1_dma.m_dest_axi_reset
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add_connection sys_dma_clk.clk axi_usdrx1_dma.m_dest_axi_clock
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# core-clock
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2017-05-12 17:40:14 +00:00
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add_instance rx_core_clk altera_clock_bridge
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2016-12-08 15:33:35 +00:00
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add_connection avl_usdrx1_xcvr.core_clk rx_core_clk.in_clk
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add_interface rx_core_clk clock source
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set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk
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# addresses
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2017-06-15 14:20:52 +00:00
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ad_cpu_interconnect 0x00010000 avl_usdrx1_xcvr.phy_reconfig_0
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ad_cpu_interconnect 0x00011000 avl_usdrx1_xcvr.phy_reconfig_1
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ad_cpu_interconnect 0x00012000 avl_usdrx1_xcvr.phy_reconfig_2
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ad_cpu_interconnect 0x00013000 avl_usdrx1_xcvr.phy_reconfig_3
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ad_cpu_interconnect 0x00014000 avl_usdrx1_xcvr.phy_reconfig_4
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ad_cpu_interconnect 0x00015000 avl_usdrx1_xcvr.phy_reconfig_5
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ad_cpu_interconnect 0x00016000 avl_usdrx1_xcvr.phy_reconfig_6
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ad_cpu_interconnect 0x00017000 avl_usdrx1_xcvr.phy_reconfig_7
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ad_cpu_interconnect 0x0001b000 avl_usdrx1_xcvr.core_pll_reconfig
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ad_cpu_interconnect 0x0001c000 avl_usdrx1_xcvr.ip_reconfig
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ad_cpu_interconnect 0x00030000 axi_usdrx1_xcvr.s_axi
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ad_cpu_interconnect 0x00040000 axi_ad9671_core_0.s_axi
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ad_cpu_interconnect 0x00050000 axi_ad9671_core_1.s_axi
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ad_cpu_interconnect 0x00060000 axi_ad9671_core_2.s_axi
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ad_cpu_interconnect 0x00070000 axi_ad9671_core_3.s_axi
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ad_cpu_interconnect 0x00080000 axi_usdrx1_dma.s_axi
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2016-12-08 15:33:35 +00:00
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# dma interconnects
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ad_dma_interconnect axi_usdrx1_dma.m_dest_axi
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# interrupts
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ad_cpu_interrupt 11 axi_usdrx1_dma.interrupt_sender
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