513 lines
16 KiB
Coq
513 lines
16 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ltc235x #(
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parameter ID = 0,
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parameter XILINX_INTEL_N = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter [0:0] LVDS_CMOS_N = 0,
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parameter LANE_0_ENABLE = 1,
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parameter LANE_1_ENABLE = 1,
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parameter LANE_2_ENABLE = 1,
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parameter LANE_3_ENABLE = 1,
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parameter LANE_4_ENABLE = 1,
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parameter LANE_5_ENABLE = 1,
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parameter LANE_6_ENABLE = 1,
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parameter LANE_7_ENABLE = 1,
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parameter EXTERNAL_CLK = 0,
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parameter LTC235X_FAMILY = 0,
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parameter NUM_CHANNELS = 8,
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parameter DATA_WIDTH = 18
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) (
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// physical data interface
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input external_clk,
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// common
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input busy,
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output lvds_cmos_n,
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// cmos
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output sdi,
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output scki,
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input scko,
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input [ 7:0] sdo,
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// lvds
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output sdi_p,
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output sdi_n,
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output scki_p,
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output scki_n,
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input scko_p,
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input scko_n,
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input sdo_p,
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input sdo_n,
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// AXI Slave Memory Map
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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// Write FIFO interface
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input adc_dovf,
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output adc_valid_0,
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output adc_valid_1,
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output adc_valid_2,
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output adc_valid_3,
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output adc_valid_4,
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output adc_valid_5,
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output adc_valid_6,
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output adc_valid_7,
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output adc_enable_0,
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output adc_enable_1,
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output adc_enable_2,
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output adc_enable_3,
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output adc_enable_4,
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output adc_enable_5,
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output adc_enable_6,
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output adc_enable_7,
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output [31:0] adc_data_0,
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output [31:0] adc_data_1,
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output [31:0] adc_data_2,
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output [31:0] adc_data_3,
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output [31:0] adc_data_4,
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output [31:0] adc_data_5,
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output [31:0] adc_data_6,
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output [31:0] adc_data_7
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);
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// localparam
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localparam [ 7:0] ACTIVE_LANES = {
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LANE_7_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_6_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_5_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_4_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_3_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_2_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_1_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_0_ENABLE == 1 ? 1'b1 : 1'b0};
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localparam [ 0:0] RD_RAW_DATA = 1'b1;
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localparam [ 0:0] CMOS_OR_LVDS_N = ~LVDS_CMOS_N[0];
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localparam [31:0] CONFIG = {18'd0, RD_RAW_DATA, 5'b0, CMOS_OR_LVDS_N, 7'b0}; // truncated value with size 45 to match size of target (32)
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// internal registers
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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// internal signals
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wire [23:0] softspan_24;
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wire [ 2:0] softspan_3[0:7];
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wire adc_valid;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire adc_clk_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s[0:8];
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wire [ 8:0] up_rack_s;
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wire [ 8:0] up_wack_s;
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// read raw, feature
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wire rd_req_s;
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wire wr_req_s;
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wire [15:0] wr_data_s;
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wire [15:0] rd_data_s;
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wire rd_valid_s;
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wire adc_rst_s;
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wire [ 7:0] adc_enable;
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wire [ 2:0] adc_status_header[0:7];
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wire [31:0] adc_data[0:7];
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// defaults
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign lvds_cmos_n = LVDS_CMOS_N[0];
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assign adc_valid_0 = adc_valid;
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assign adc_valid_1 = adc_valid;
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assign adc_valid_2 = adc_valid;
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assign adc_valid_3 = adc_valid;
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assign adc_valid_4 = adc_valid;
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assign adc_valid_5 = adc_valid;
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assign adc_valid_6 = adc_valid;
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assign adc_valid_7 = adc_valid;
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assign adc_enable_0 = adc_enable[0];
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assign adc_enable_1 = adc_enable[1];
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assign adc_enable_2 = adc_enable[2];
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assign adc_enable_3 = adc_enable[3];
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assign adc_enable_4 = adc_enable[4];
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assign adc_enable_5 = adc_enable[5];
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assign adc_enable_6 = adc_enable[6];
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assign adc_enable_7 = adc_enable[7];
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assign adc_data_0 = adc_data[0];
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assign adc_data_1 = adc_data[1];
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assign adc_data_2 = adc_data[2];
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assign adc_data_3 = adc_data[3];
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assign adc_data_4 = adc_data[4];
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assign adc_data_5 = adc_data[5];
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assign adc_data_6 = adc_data[6];
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assign adc_data_7 = adc_data[7];
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generate
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if (NUM_CHANNELS == 8) begin
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assign softspan_24 = {softspan_3[7], softspan_3[6], softspan_3[5], softspan_3[4], softspan_3[3], softspan_3[2], softspan_3[1], softspan_3[0]};
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end else if (NUM_CHANNELS == 4) begin
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assign softspan_24 = {softspan_3[3], softspan_3[2], softspan_3[1], softspan_3[0], 12'b0};
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end else begin
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assign softspan_24 = {softspan_3[1], softspan_3[0], 18'b0};
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end
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endgenerate
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// processor read/write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= |up_wack_s;
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up_rack <= |up_rack_s;
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up_rdata <= up_rdata_s[0] |
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up_rdata_s[1] |
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up_rdata_s[2] |
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up_rdata_s[3] |
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up_rdata_s[4] |
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up_rdata_s[5] |
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up_rdata_s[6] |
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up_rdata_s[7] |
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up_rdata_s[8];
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end
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end
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// CMOS/LVDS INTERFACE
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generate
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if (EXTERNAL_CLK == 1'b1) begin
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assign adc_clk_s = external_clk;
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end else begin
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assign adc_clk_s = up_clk;
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end
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if (LVDS_CMOS_N == 1) begin
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axi_ltc235x_lvds #(
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.XILINX_INTEL_N (XILINX_INTEL_N),
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.LTC235X_FAMILY (LTC235X_FAMILY),
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.NUM_CHANNELS (NUM_CHANNELS),
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.DATA_WIDTH (DATA_WIDTH)
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) i_ltc235x_lvds (
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.rst (adc_rst_s),
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.clk (adc_clk_s),
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.adc_enable (adc_enable),
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.softspan_next (softspan_24),
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.scki_p (scki_p),
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.scki_n (scki_n),
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.sdi_p (sdi_p),
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.sdi_n (sdi_n),
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.scko_p (scko_p),
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.scko_n (scko_n),
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.sdo_p (sdo_p),
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.sdo_n (sdo_n),
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.busy (busy),
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.adc_ch0_id (adc_status_header[0]),
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.adc_ch1_id (adc_status_header[1]),
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.adc_ch2_id (adc_status_header[2]),
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.adc_ch3_id (adc_status_header[3]),
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.adc_ch4_id (adc_status_header[4]),
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.adc_ch5_id (adc_status_header[5]),
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.adc_ch6_id (adc_status_header[6]),
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.adc_ch7_id (adc_status_header[7]),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_2 (adc_data_2),
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.adc_data_3 (adc_data_3),
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.adc_data_4 (adc_data_4),
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.adc_data_5 (adc_data_5),
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.adc_data_6 (adc_data_6),
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.adc_data_7 (adc_data_7),
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.adc_softspan_0 (),
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.adc_softspan_1 (),
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.adc_softspan_2 (),
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.adc_softspan_3 (),
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.adc_softspan_4 (),
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.adc_softspan_5 (),
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.adc_softspan_6 (),
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.adc_softspan_7 (),
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.adc_valid (adc_valid));
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end else begin
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axi_ltc235x_cmos #(
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.LTC235X_FAMILY (LTC235X_FAMILY),
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.ACTIVE_LANES (ACTIVE_LANES),
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.NUM_CHANNELS (NUM_CHANNELS),
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.DATA_WIDTH (DATA_WIDTH)
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) i_ltc235x_cmos (
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.rst (adc_rst_s),
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.clk (adc_clk_s),
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.adc_enable (adc_enable),
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.softspan_next (softspan_24),
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.scki (scki),
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.sdi (sdi),
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.scko (scko),
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.sdo (sdo),
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.busy (busy),
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.adc_ch0_id (adc_status_header[0]),
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.adc_ch1_id (adc_status_header[1]),
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.adc_ch2_id (adc_status_header[2]),
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.adc_ch3_id (adc_status_header[3]),
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.adc_ch4_id (adc_status_header[4]),
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.adc_ch5_id (adc_status_header[5]),
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.adc_ch6_id (adc_status_header[6]),
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.adc_ch7_id (adc_status_header[7]),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_2 (adc_data_2),
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.adc_data_3 (adc_data_3),
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.adc_data_4 (adc_data_4),
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.adc_data_5 (adc_data_5),
|
||
|
|
.adc_data_6 (adc_data_6),
|
||
|
|
.adc_data_7 (adc_data_7),
|
||
|
|
.adc_softspan_0 (),
|
||
|
|
.adc_softspan_1 (),
|
||
|
|
.adc_softspan_2 (),
|
||
|
|
.adc_softspan_3 (),
|
||
|
|
.adc_softspan_4 (),
|
||
|
|
.adc_softspan_5 (),
|
||
|
|
.adc_softspan_6 (),
|
||
|
|
.adc_softspan_7 (),
|
||
|
|
.adc_valid (adc_valid));
|
||
|
|
end
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
// regmap adc channels
|
||
|
|
|
||
|
|
generate
|
||
|
|
genvar i;
|
||
|
|
for (i = 0; i < NUM_CHANNELS; i=i+1) begin : regmap_channels
|
||
|
|
up_adc_channel #(
|
||
|
|
.CHANNEL_ID(i)
|
||
|
|
) i_up_adc_channel (
|
||
|
|
.adc_clk (adc_clk_s),
|
||
|
|
.adc_rst (adc_rst_s),
|
||
|
|
.adc_enable (adc_enable[i]),
|
||
|
|
.adc_iqcor_enb (),
|
||
|
|
.adc_dcfilt_enb (),
|
||
|
|
.adc_dfmt_se (),
|
||
|
|
.adc_dfmt_type (),
|
||
|
|
.adc_dfmt_enable (),
|
||
|
|
.adc_dcfilt_offset (),
|
||
|
|
.adc_dcfilt_coeff (),
|
||
|
|
.adc_iqcor_coeff_1 (),
|
||
|
|
.adc_iqcor_coeff_2 (),
|
||
|
|
.adc_pnseq_sel (),
|
||
|
|
.adc_data_sel (),
|
||
|
|
.adc_pn_err (1'b0),
|
||
|
|
.adc_pn_oos (1'b0),
|
||
|
|
.adc_or (1'b0),
|
||
|
|
.adc_read_data (adc_data[i]),
|
||
|
|
.adc_status_header({5'd0, adc_status_header[i]}),
|
||
|
|
.adc_crc_err(1'b0),
|
||
|
|
.adc_softspan (softspan_3[i]),
|
||
|
|
.up_adc_crc_err (),
|
||
|
|
.up_adc_pn_err (),
|
||
|
|
.up_adc_pn_oos (),
|
||
|
|
.up_adc_or (),
|
||
|
|
.up_usr_datatype_be (),
|
||
|
|
.up_usr_datatype_signed (),
|
||
|
|
.up_usr_datatype_shift (),
|
||
|
|
.up_usr_datatype_total_bits (),
|
||
|
|
.up_usr_datatype_bits (),
|
||
|
|
.up_usr_decimation_m (),
|
||
|
|
.up_usr_decimation_n (),
|
||
|
|
.adc_usr_datatype_be (1'b0),
|
||
|
|
.adc_usr_datatype_signed (1'b1),
|
||
|
|
.adc_usr_datatype_shift (8'd0),
|
||
|
|
.adc_usr_datatype_total_bits (8'd32),
|
||
|
|
.adc_usr_datatype_bits (8'd32),
|
||
|
|
.adc_usr_decimation_m (16'd1),
|
||
|
|
.adc_usr_decimation_n (16'd1),
|
||
|
|
.up_rstn (up_rstn),
|
||
|
|
.up_clk (up_clk),
|
||
|
|
.up_wreq (up_wreq_s),
|
||
|
|
.up_waddr (up_waddr_s),
|
||
|
|
.up_wdata (up_wdata_s),
|
||
|
|
.up_wack (up_wack_s[i]),
|
||
|
|
.up_rreq (up_rreq_s),
|
||
|
|
.up_raddr (up_raddr_s),
|
||
|
|
.up_rdata (up_rdata_s[i]),
|
||
|
|
.up_rack (up_rack_s[i]));
|
||
|
|
end
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
// up adc common
|
||
|
|
|
||
|
|
up_adc_common #(
|
||
|
|
.ID(ID),
|
||
|
|
.CONFIG(CONFIG)
|
||
|
|
) i_up_adc_common (
|
||
|
|
.mmcm_rst (),
|
||
|
|
.adc_clk (adc_clk_s),
|
||
|
|
.adc_rst (adc_rst_s),
|
||
|
|
.adc_r1_mode (),
|
||
|
|
.adc_ddr_edgesel (),
|
||
|
|
.adc_pin_mode (),
|
||
|
|
.adc_status ('h1),
|
||
|
|
.adc_sync_status (1'b1),
|
||
|
|
.adc_status_ovf (adc_dovf),
|
||
|
|
.adc_clk_ratio (32'd1),
|
||
|
|
.adc_start_code (),
|
||
|
|
.adc_sref_sync (),
|
||
|
|
.adc_sync (),
|
||
|
|
.adc_ext_sync_arm(),
|
||
|
|
.adc_ext_sync_disarm(),
|
||
|
|
.adc_ext_sync_manual_req(),
|
||
|
|
.adc_num_lanes(),
|
||
|
|
.adc_custom_control(),
|
||
|
|
.adc_crc_enable(),
|
||
|
|
.adc_sdr_ddr_n(),
|
||
|
|
.adc_symb_op(),
|
||
|
|
.adc_symb_8_16b(),
|
||
|
|
.up_pps_rcounter (32'b0),
|
||
|
|
.up_pps_status (1'b0),
|
||
|
|
.up_pps_irq_mask (),
|
||
|
|
.up_adc_r1_mode(),
|
||
|
|
.up_adc_ce (),
|
||
|
|
.up_status_pn_err (1'b0),
|
||
|
|
.up_status_pn_oos (1'b0),
|
||
|
|
.up_status_or (1'b0),
|
||
|
|
.up_drp_sel (),
|
||
|
|
.up_drp_wr (),
|
||
|
|
.up_drp_addr (),
|
||
|
|
.up_drp_wdata (),
|
||
|
|
.up_drp_rdata (32'd0),
|
||
|
|
.up_drp_ready (1'd0),
|
||
|
|
.up_drp_locked (1'd1),
|
||
|
|
.adc_config_wr (),
|
||
|
|
.adc_config_ctrl (),
|
||
|
|
.adc_config_rd (32'd0),
|
||
|
|
.adc_ctrl_status (1'd0),
|
||
|
|
.up_usr_chanmax_out (),
|
||
|
|
.up_usr_chanmax_in (8),
|
||
|
|
.up_adc_gpio_in (32'b0),
|
||
|
|
.up_adc_gpio_out (),
|
||
|
|
.up_rstn (up_rstn),
|
||
|
|
.up_clk (up_clk),
|
||
|
|
.up_wreq (up_wreq_s),
|
||
|
|
.up_waddr (up_waddr_s),
|
||
|
|
.up_wdata (up_wdata_s),
|
||
|
|
.up_wack (up_wack_s[8]),
|
||
|
|
.up_rreq (up_rreq_s),
|
||
|
|
.up_raddr (up_raddr_s),
|
||
|
|
.up_rdata (up_rdata_s[8]),
|
||
|
|
.up_rack (up_rack_s[8]));
|
||
|
|
|
||
|
|
// up bus interface
|
||
|
|
|
||
|
|
up_axi #(
|
||
|
|
.AXI_ADDRESS_WIDTH (16)
|
||
|
|
) i_up_axi (
|
||
|
|
.up_rstn (up_rstn),
|
||
|
|
.up_clk (up_clk),
|
||
|
|
.up_axi_awvalid (s_axi_awvalid),
|
||
|
|
.up_axi_awaddr (s_axi_awaddr),
|
||
|
|
.up_axi_awready (s_axi_awready),
|
||
|
|
.up_axi_wvalid (s_axi_wvalid),
|
||
|
|
.up_axi_wdata (s_axi_wdata),
|
||
|
|
.up_axi_wstrb (s_axi_wstrb),
|
||
|
|
.up_axi_wready (s_axi_wready),
|
||
|
|
.up_axi_bvalid (s_axi_bvalid),
|
||
|
|
.up_axi_bresp (s_axi_bresp),
|
||
|
|
.up_axi_bready (s_axi_bready),
|
||
|
|
.up_axi_arvalid (s_axi_arvalid),
|
||
|
|
.up_axi_araddr (s_axi_araddr),
|
||
|
|
.up_axi_arready (s_axi_arready),
|
||
|
|
.up_axi_rvalid (s_axi_rvalid),
|
||
|
|
.up_axi_rresp (s_axi_rresp),
|
||
|
|
.up_axi_rdata (s_axi_rdata),
|
||
|
|
.up_axi_rready (s_axi_rready),
|
||
|
|
.up_wreq (up_wreq_s),
|
||
|
|
.up_waddr (up_waddr_s),
|
||
|
|
.up_wdata (up_wdata_s),
|
||
|
|
.up_wack (up_wack),
|
||
|
|
.up_rreq (up_rreq_s),
|
||
|
|
.up_raddr (up_raddr_s),
|
||
|
|
.up_rdata (up_rdata),
|
||
|
|
.up_rack (up_rack));
|
||
|
|
|
||
|
|
endmodule
|