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pluto_hdl_adi/library/jesd204/axi_jesd204_rx/Makefile

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Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../../common/up_axi.v
M_DEPS += ../../common/up_clock_mon.v
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += axi_jesd204_rx.v
M_DEPS += axi_jesd204_rx_constr.xdc
M_DEPS += axi_jesd204_rx_ip.tcl
M_DEPS += jesd204_up_ilas_mem.v
M_DEPS += jesd204_up_rx.v
M_DEPS += jesd204_up_rx_lane.v
M_DEPS += ../../jesd204/axi_jesd204_common/axi_jesd204_common.xpr
M_DEPS += ../../util_cdc/util_cdc.xpr
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all dep clean clean-all
all: dep axi_jesd204_rx.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_jesd204_rx.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_jesd204_rx_ip.tcl >> axi_jesd204_rx_ip.log 2>&1
dep:
Make: Use $(MAKE) for recursive make commands This commit should resolve the issue #64. Recursive make commands should always use the variable MAKE, not the explicit command name ‘make’.
2018-03-06 12:36:06 +00:00
$(MAKE) -C ../../jesd204/axi_jesd204_common/
$(MAKE) -C ../../util_cdc/
$(MAKE) -C ../../jesd204/interfaces/
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
####################################################################################
####################################################################################