zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/daq3/zcu102/system_bd.tcl

78 lines
3.0 KiB
Tcl
Raw Normal View History

daq3/zcu102: Initial commit
2017-07-31 11:21:56 +00:00
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## FIFO depth is 8Mb - 500k samples
set dac_fifo_address_width 16
daq3/zcu102: Initial commit
2017-07-31 11:21:56 +00:00
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
## NOTE: With this configuration the #36Kb BRAM utilization is at ~28%
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
daq3/zcu102: Initial commit
2017-07-31 11:21:56 +00:00
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source ../common/daq3_bd.tcl
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
daq3/zcu102: Add custom configuration for CPLL To support 12.33 Gbps add a custom configuration for the CPLLs.
2018-10-02 15:43:47 +00:00
# configure the CPLL's to support 12.33Gbps
ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG0 0x03fe
ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG1 0x0021
ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG2 0x0203
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
create_bd_port -dir I dac_fifo_bypass
daq3/zcu102: Initial commit
2017-07-31 11:21:56 +00:00
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20
daq3: ZCU102: Fix AXI_ADXCVR IPs XCVR_TYPE parameter
2018-06-08 10:56:22 +00:00
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
ad_ip_parameter axi_ad9152_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad9152_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9680_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9680_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_instance clk_wiz dma_clk_wiz
ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
ad_ip_instance proc_sys_reset sys_dma_rstgen
ad_connect sys_cpu_clk dma_clk_wiz/clk_in1
ad_connect sys_cpu_resetn dma_clk_wiz/resetn
ad_connect sys_dma_clk dma_clk_wiz/clk_out1
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
ad_connect sys_cpu_resetn sys_dma_rstgen/ext_reset_in
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
ad_connect sys_dma_clk axi_ad9152_fifo/dma_clk
ad_connect sys_dma_reset axi_ad9152_fifo/dma_rst
ad_connect sys_dma_clk axi_ad9152_dma/m_axis_aclk
ad_connect sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
ad_connect axi_ad9152_fifo/bypass dac_fifo_bypass
ad_connect sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_dma/fifo_wr_clk util_daq3_xcvr/rx_out_clk_0
daq3: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-04 10:41:11 +00:00
ad_connect axi_ad9680_cpack/packed_fifo_wr axi_ad9680_dma/fifo_wr
daq3: ZCU102: Remove Offload FIFO for ADC path. DAC FIFO cannot be increased because of timing violations
2018-07-11 07:23:50 +00:00
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_dma_clk axi_ad9680_dma/m_dest_axi
ad_mem_hp3_interconnect sys_dma_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_dma_clk axi_ad9152_dma/m_src_axi