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pluto_hdl_adi/library/axi_dmac/axi_dmac_ip.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# ip
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
global VIVADO_IP_LIBRARY
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_ip_create axi_dmac
adi_ip_files axi_dmac [list \
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
"$ad_hdl_dir/library/common/up_axi.v" \
axi_dmac: renamed .h files to .vh Vivado recognises .h files as C header files, the expected extension for Verilog Header is .vh This causes issues in simulating block designs since these files won't be exported for the simulation even if they are part of the simulation fileset.
2018-06-28 11:14:14 +00:00
"inc_id.vh" \
"resp.vh" \
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
"axi_dmac_burst_memory.v" \
axi_dmac: Split register map into separate sub-module Split the register map code into a separate sub-module instead of having it as part of the top-level axi_dmac.v file. This makes it easier to component test the register map behavior independently from the DMA transfer logic. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
"axi_dmac_regmap.v" \
"axi_dmac_regmap_request.v" \
axi_dmac: Rework transfer shutdown The DMAC allows a transfer to be aborted. When a transfer is aborted the DMAC shuts down as fast as possible while still completing any pending transactions as required by the protocol specifications of the port. E.g. for AXI-MM this means to complete all outstanding bursts. Once the DMAC has entered an idle state a special synchronization signal is send to all modules. This synchronization signal instructs them to flush the pipeline and remove any stale data and metadata associated with the aborted transfer. Once all data has been flushed the DMAC enters the shutdown state and is ready for the next transfer. In addition each module has a reset that resets the modules state and is used at system startup to bring them into a consistent state. Re-work the shutdown process to instead of flushing the pipeline re-use the startup reset signal also for shutdown. To manage the reset signal generation introduce the reset manager module. It contains a state machine that will assert the reset signals in the correct order and for the appropriate duration in case of a transfer shutdown. The reset signal is asserted in all domains until it has been asserted for at least 4 clock cycles in the slowest domain. This ensures that the reset signal is not de-asserted in the faster domains before the slower domains have had a chance to process the reset signal. In addition the reset signal is de-asserted in the opposite direction of the data flow. This ensures that the data sink is ready to receive data before the data source can start sending data. This simplifies the internal handshaking. This approach has multiple advantages. * Issuing a reset and removing all state takes less time than explicitly flushing one sample per clock cycle at a time. * It simplifies the logic in the faster clock domains at the expense of more complicated logic in the slower control clock domain. This allows for higher fMax on the data paths. * Less signals to synchronize from the control domain to the data domains The implementation of the pause mode has also slightly changed. Pause is now a simple disable of the data domains. When the transfer is resumed after a pause the data domains are re-enabled and continue at their previous state. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-21 14:02:44 +00:00
"axi_dmac_reset_manager.v" \
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
"axi_dmac_resize_dest.v" \
"axi_dmac_resize_src.v" \
axi_dmac: preparation work for reporting length of partial transfers Length of partial transfers are stored in a queue for SW reads. The presence of partial transfer is indicated by a status bit. The reporting can be enabled by a control bit. The progress of any transfer can be followed by a debug register.
2018-08-10 14:47:21 +00:00
"axi_dmac_response_manager.v" \
axi_dmac: Split transfer handling into separate sub-module Move the transfer logic, including the 2d module, into its own sub-module. This allows testing of the full transfer logic independently of the register map logic. The top-level module now only instantiates the register map and transfer module, but does not have any logic on its own. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
"axi_dmac_transfer.v" \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
"address_generator.v" \
"data_mover.v" \
"request_arb.v" \
"request_generator.v" \
"response_handler.v" \
"axi_register_slice.v" \
library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer Update the file according to HDL guideline. Replace all occurrences of 2d_transfer with dmac_2d_transfer. Update axi_dmac/Makefile.
2022-03-31 11:33:10 +00:00
"dmac_2d_transfer.v" \
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
"dest_axi_mm.v" \
"dest_axi_stream.v" \
"dest_fifo_inf.v" \
"src_axi_mm.v" \
"src_axi_stream.v" \
"src_fifo_inf.v" \
"splitter.v" \
"response_generator.v" \
"axi_dmac.v" \
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
"axi_dmac_constr.ttcl" \
axi_dmac: ttcl file support for simulation When creating a block design targeted for simulation, in the testbench it is useful to know the parameters of the sub components (e.g DMAC) Xilinx's way to pass the parameters to the testbench in case of it's AXI verification IP is through package files. We will do the same for the DMAC. The package file can be generated from template files (ttcl). These will be added only to the simulation file set of the project and won't affect synthesis.
2018-05-04 09:27:43 +00:00
"axi_dmac_pkg_sv.ttcl" \
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
"bd/bd.tcl" ]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_ip_properties axi_dmac
axi_dmac: Fix memory map infer issues Define an address space reference to the m_dest_axi and m_src_axi interfaces.
2017-01-19 13:09:07 +00:00
adi_ip_infer_mm_interfaces axi_dmac
axi_dmac: Generate per core instance constraint file When having multiple DMA cores sharing the same constraint file Vivado seems to apply the constraints from the first core to all the other cores when re-running synthesis and implementation from within the Vivado GUI. This causes wrong timing constraints if the DMA cores have different configurations. To avoid this issue use a TTCL template that generates a custom constraint file for each DMA core instance. This also allows us to drop the asynchronous clock detection hack from the constraint file and move it to the template and only generate the CDC constraints if the clock domains are asynchronous. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 16:58:40 +00:00
adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
axi_dmac: ttcl file support for simulation When creating a block design targeted for simulation, in the testbench it is useful to know the parameters of the sub components (e.g DMAC) Xilinx's way to pass the parameters to the testbench in case of it's AXI verification IP is through package files. We will do the same for the DMAC. The package file can be generated from template files (ttcl). These will be added only to the simulation file set of the project and won't affect synthesis.
2018-05-04 09:27:43 +00:00
adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl"
axi_dmac: Add support for auto-detecting asynchronous clock configuration Add support for querying the clock domains of the clock pins for the axi_dmac controller. This allows the core to automatically figure out whether its different parts run in different clock domains or not and setup the configuration parameters accordingly. Being able to auto-detect those configuration parameters makes the core easier to use and also avoids accidental misconfiguration. It is still possible to automatically overwrite the configuration parameters by hand if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 07:48:26 +00:00
adi_ip_bd axi_dmac "bd/bd.tcl"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
library: Add link to wiki for IPs
2021-10-20 15:08:35 +00:00
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dmac} [ipx::current_core]
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
axi_dmac: Set IP core name and description Add a human readable name and descriptor for the AXI DMAC core.This string will appear in various places e.g. like the IP catalog. This is a purely cosmetic change. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 12:33:31 +00:00
set_property display_name "ADI AXI DMA Controller" [ipx::current_core]
set_property description "ADI AXI DMA Controller" [ipx::current_core]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"s_axis_ready" "TREADY"} \
{"s_axis_valid" "TVALID"} \
{"s_axis_data" "TDATA"} \
axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle The unused AXI stream signals have to be added to the AXIS interface so they don't hang loose on the IP in the block design.
2019-07-08 07:37:00 +00:00
{"s_axis_strb" "TSTRB"} \
{"s_axis_keep" "TKEEP"} \
{"s_axis_user" "TUSER"} \
{"s_axis_id" "TID"} \
{"s_axis_dest" "TDEST"} \
{"s_axis_last" "TLAST"}]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_add_bus_clock "s_axis_aclk" "s_axis"
adi_add_bus "m_axis" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"m_axis_ready" "TREADY"} \
{"m_axis_valid" "TVALID"} \
axi_dmac: Include TLAST in AXIS slave port Bundle the TLAST signal in with the other AXIS slave signals to enable easier connection between AXIS devices that use TLAST Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-12-20 00:39:30 +00:00
{"m_axis_data" "TDATA"} \
axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle The unused AXI stream signals have to be added to the AXIS interface so they don't hang loose on the IP in the block design.
2019-07-08 07:37:00 +00:00
{"m_axis_strb" "TSTRB"} \
{"m_axis_keep" "TKEEP"} \
{"m_axis_user" "TUSER"} \
{"m_axis_id" "TID"} \
{"m_axis_dest" "TDEST"} \
{"m_axis_last" "TLAST"}]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_add_bus_clock "m_axis_aclk" "m_axis"
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_set_bus_dependency "m_src_axi" "m_src_axi" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_set_bus_dependency "s_axis" "s_axis" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_set_bus_dependency "m_axis" "m_axis" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_set_ports_dependency "fifo_rd" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
axi_dmac: diagnostic interface in bursts This change adds a diagnostic interface to the DMAC core. The interface exposes internal information about the core, information which can't be exposed through AXI registers due the latency and update rate. Such information is the fullness of the internal buffer. For this is exposed in bursts and is driven from the destination clock domain, as this is reflected in its name. The signal has a fixed size and is dimensioned by taking in account the supported maximum number of bursts of 128.
2018-06-07 13:20:27 +00:00
adi_set_ports_dependency "dest_diag_level_bursts" \
"(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
cosmetics: Change Altera to Intel in comments
2018-08-14 12:48:32 +00:00
# These are in the design to keep the Intel tools happy which can't handle
axi_dmac: Disable dummy AXI ports for Xilinx IPI The memory mapped AXI interfaces for the AXI-DMAC are uni-directional. Which means they are either write-only or read-only. Unfortunately the Altera tools can't handle this, so we had to add dummy signals for the other direction. The Xilinx tools on the other hand handle uni-directional AXI interfaces and in fact IPI can do a better job and use less resources when creating the AXI interconnects when it knows that the interface is uni-directional. So always disable the dummy ports for the IPI package. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 16:12:04 +00:00
# uni-directional AXI interfaces. The Xilinx tools can and do a better job when
axi_dmac: Disable dummy AXI ports for Xilinx IPI The memory mapped AXI interfaces for the AXI-DMAC are uni-directional. Which means they are either write-only or read-only. Unfortunately the Altera tools can't handle this, so we had to add dummy signals for the other direction. The Xilinx tools on the other hand handle uni-directional AXI interfaces and in fact IPI can do a better job and use less resources when creating the AXI interconnects when it knows that the interface is uni-directional. So always disable the dummy ports for the IPI package. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 16:12:04 +00:00
# they know that the interface is uni-directional, so disable the ports.
set dummy_axi_ports [list \
"m_dest_axi_arvalid" \
"m_dest_axi_arready" \
"m_dest_axi_araddr" \
"m_dest_axi_arlen" \
"m_dest_axi_arsize" \
"m_dest_axi_arburst" \
"m_dest_axi_arcache" \
"m_dest_axi_arprot" \
"m_dest_axi_rready" \
"m_dest_axi_rvalid" \
"m_dest_axi_rresp" \
"m_dest_axi_rdata" \
"m_src_axi_awvalid" \
"m_src_axi_awready" \
"m_src_axi_awvalid" \
"m_src_axi_awaddr" \
"m_src_axi_awlen" \
"m_src_axi_awsize" \
"m_src_axi_awburst" \
"m_src_axi_awcache" \
"m_src_axi_awprot" \
"m_src_axi_wvalid" \
"m_src_axi_wready" \
"m_src_axi_wvalid" \
"m_src_axi_wdata" \
"m_src_axi_wstrb" \
"m_src_axi_wlast" \
"m_src_axi_bready" \
"m_src_axi_bvalid" \
"m_src_axi_bresp" \
]
cosmetics: Change Altera to Intel in comments
2018-08-14 12:48:32 +00:00
# These are in the design to keep the Intel tools happy which require
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
# certain signals in AXI3 mode even if these are defined as optinal in the standard.
lappend dummy_axi_ports \
"m_dest_axi_awid" \
"m_dest_axi_awlock" \
"m_dest_axi_wid" \
"m_dest_axi_bid" \
"m_dest_axi_arid" \
"m_dest_axi_arlock" \
"m_dest_axi_rid" \
"m_dest_axi_rlast" \
"m_src_axi_arid" \
"m_src_axi_arlock" \
"m_src_axi_rid" \
"m_src_axi_awid" \
"m_src_axi_awlock" \
"m_src_axi_wid" \
"m_src_axi_bid"
axi_dmac: Disable dummy AXI ports for Xilinx IPI The memory mapped AXI interfaces for the AXI-DMAC are uni-directional. Which means they are either write-only or read-only. Unfortunately the Altera tools can't handle this, so we had to add dummy signals for the other direction. The Xilinx tools on the other hand handle uni-directional AXI interfaces and in fact IPI can do a better job and use less resources when creating the AXI interconnects when it knows that the interface is uni-directional. So always disable the dummy ports for the IPI package. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 16:12:04 +00:00
foreach p $dummy_axi_ports {
axi_dmac: Fix dummy port enablement dependency It seems that in the latest version a constant of "0" is no longer a valid enablement dependency and "false" has be used instead. Not setting the enablement dependency correctly results in the AXI port to be assumed to be read-write rather than just read or write. This will generate unnecessary logic for example in interconnects to which the DMA controller is connected. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-14 14:56:31 +00:00
adi_set_ports_dependency $p "false"
axi_dmac: Disable dummy AXI ports for Xilinx IPI The memory mapped AXI interfaces for the AXI-DMAC are uni-directional. Which means they are either write-only or read-only. Unfortunately the Altera tools can't handle this, so we had to add dummy signals for the other direction. The Xilinx tools on the other hand handle uni-directional AXI interfaces and in fact IPI can do a better job and use less resources when creating the AXI interconnects when it knows that the interface is uni-directional. So always disable the dummy ports for the IPI package. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 16:12:04 +00:00
}
axi_dmac: Fix memory map infer issues Define an address space reference to the m_dest_axi and m_src_axi interfaces.
2017-01-19 13:09:07 +00:00
set_property master_address_space_ref m_dest_axi \
[ipx::get_bus_interfaces m_dest_axi \
-of_objects [ipx::current_core]]
set_property master_address_space_ref m_src_axi \
[ipx::get_bus_interfaces m_src_axi \
-of_objects [ipx::current_core]]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_add_bus "fifo_wr" "slave" \
"analog.com:interface:fifo_wr_rtl:1.0" \
"analog.com:interface:fifo_wr:1.0" \
{ \
{"fifo_wr_en" "EN"} \
{"fifo_wr_din" "DATA"} \
{"fifo_wr_overflow" "OVERFLOW"} \
{"fifo_wr_sync" "SYNC"} \
{"fifo_wr_xfer_req" "XFER_REQ"} \
}
adi_add_bus_clock "fifo_wr_clk" "fifo_wr"
adi_set_bus_dependency "fifo_wr" "fifo_wr" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_add_bus "fifo_rd" "slave" \
"analog.com:interface:fifo_rd_rtl:1.0" \
"analog.com:interface:fifo_rd:1.0" \
{
{"fifo_rd_en" "EN"} \
{"fifo_rd_dout" "DATA"} \
{"fifo_rd_valid" "VALID"} \
{"fifo_rd_underflow" "UNDERFLOW"} \
}
adi_add_bus_clock "fifo_rd_clk" "fifo_rd"
adi_set_bus_dependency "fifo_rd" "fifo_rd" \
axi_dmac: Parameter changes Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 13:05:22 +00:00
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
axi_dmac: Add limited TLAST support for streaming AXI source interface Add some limit TLAST support for the streaming AXI source interface. An asserted TLAST signal marks the end of a packet and the following data beat is the first beat for the next packet. Currently the DMAC does not support for completing a transfer before all requested bytes have been transferred. So the way this limited TLAST support is implemented is by filling the remainder of the buffer with 0x00. While the DMAC is busy filling the buffer with zeros back-pressure is asserted on the external streaming AXI interface by keeping TREADY de-asserted. The end of a buffer is marked by a transfer that has the last bit set in the FLAGS control register. In the future we might add support for transfer completion before all requested bytes have been transferred. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-12-07 17:31:10 +00:00
foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" \
"s_axis_valid" "s_axis_data" "s_axis_last" "m_axis_ready" \
"fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} {
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property DRIVER_VALUE "0" [ipx::get_ports $port]
}
foreach port {"s_axis_user" "fifo_wr_sync"} {
set_property DRIVER_VALUE "1" [ipx::get_ports $port]
}
axi_dmac: infer interrupt line for Xilinx projects The interrupt controller from Microblaze based projects requires that all its inputs have attributes which define the sensitivity of the interrupt line. Other case it defaults to EDGE_RISING which is not the case for DMAC, leading to incorrect interrupt reporting and handling in case of such projects.
2019-04-24 08:45:19 +00:00
# Infer interrupt
ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
set cc [ipx::current_core]
axi_dmac: Indicate that the core does not issue narrow AXI bursts The axi_dmac core does not issue narrow AXI bursts. Indicate this by setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master interfaces. This allows connected slaves to know that they will not receive narrow bursts, which allows them to disable support for it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:43:42 +00:00
# The core does not issue narrow bursts
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
foreach intf [ipx::get_bus_interfaces m_*_axi -of_objects $cc] {
axi_dmac: Indicate that the core does not issue narrow AXI bursts The axi_dmac core does not issue narrow AXI bursts. Indicate this by setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master interfaces. This allows connected slaves to know that they will not receive narrow bursts, which allows them to disable support for it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 09:43:42 +00:00
set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf]
set_property "VALUE" "0" $para
}
axi_dmac: List valid store-and-forward memory sizes For correct operation the store-and-forward memory size must be a power-of-two in the range of 2 to 32. This is simple enough so we can list all values and let the IP Integrator and QSYS perform proper validation of the parameter. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-30 07:27:59 +00:00
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" "2 4 8 16 32" \
] \
[ipx::get_user_parameters FIFO_SIZE -of_objects $cc]
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "8" \
"value_validation_range_maximum" "32" \
] \
[ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc]
foreach {k v} { \
"ASYNC_CLK_REQ_SRC" "true" \
"ASYNC_CLK_SRC_DEST" "true" \
"ASYNC_CLK_DEST_REQ" "true" \
"CYCLIC" "false" \
"DMA_2D_TRANSFER" "false" \
"SYNC_TRANSFER_START" "false" \
"AXI_SLICE_SRC" "false" \
"AXI_SLICE_DEST" "false" \
axi_dmac: Make debug register optional The debug registers are useful during development but are rarely used in a production design. Add a option that allows to disable them, this reduces the resource utilization of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 14:00:51 +00:00
"DISABLE_DEBUG_REGISTERS" "false" \
axi_dmac: diagnostic interface in bursts This change adds a diagnostic interface to the DMAC core. The interface exposes internal information about the core, information which can't be exposed through AXI registers due the latency and update rate. Such information is the fullness of the internal buffer. For this is exposed in bursts and is driven from the destination clock domain, as this is reflected in its name. The signal has a fixed size and is dimensioned by taking in account the supported maximum number of bursts of 128.
2018-06-07 13:20:27 +00:00
"ENABLE_DIAGNOSTICS_IF" "false" \
axi_dmac: Add parameter controlling AWCACHE On architectures with ports that support cache coherency, the AWCACHE signal must be set to indicate that transactions are cached. This patch adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
2022-05-05 08:35:34 +00:00
"CACHE_COHERENT_DEST" "false" \
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
} { \
set_property -dict [list \
"value_format" "bool" \
"value" $v \
] \
[ipx::get_user_parameters $k -of_objects $cc]
set_property -dict [list \
"value_format" "bool" \
"value" $v \
] \
[ipx::get_hdl_parameters $k -of_objects $cc]
}
set_property -dict [list \
"enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \
] \
[ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc]
foreach dir {"SRC" "DEST"} {
set_property -dict [list \
"value_validation_type" "list" \
axi_dmac: Allow wider FIFO/AXI Stream interface On large projects with multiple channels the databus on the FIFO/AXI stream interface can get wider that 1024 bits. This commit allows a wider range for all the interfaces, in case for the memory mapped interfaces where the range is 32-1024 the user selects a bus width out of range that will be handled by the IPI.
2021-02-19 08:11:34 +00:00
"value_validation_list" "16 32 64 128 256 512 1024 2048" \
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
] \
[ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc]
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \
"enablement_tcl_expr" "\$DMA_TYPE_${dir} == 0" \
] \
[ipx::get_user_parameters DMA_AXI_PROTOCOL_${dir} -of_objects $cc]
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" { \
"Memory-Mapped AXI" "0" \
"Streaming AXI" "1" \
"FIFO Interface" "2" \
} \
] \
[ipx::get_user_parameters DMA_TYPE_${dir} -of_objects $cc]
}
axi_dmac: Beautify IPI GUI Group the axi_dmac parameters by function and provide a human readable name for the IPI GUI. This makes it easier to understand what parameter does what when using the IPI GUI to configure the core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:58:32 +00:00
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
set g [ipgui::add_group -name {DMA Endpoint Configuration} -component $cc \
-parent $page0 -display_name {DMA Endpoint Configuration} \
-layout "horizontal"]
set src_group [ipgui::add_group -name {Source} -component $cc -parent $g \
-display_name {Source}]
set dest_group [ipgui::add_group -name {Destination} -component $cc -parent $g \
-display_name {Destination}]
foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] {
set p [ipgui::get_guiparamspec -name "DMA_TYPE_${dir}" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $group
set_property -dict [list \
"widget" "comboBox" \
"display_name" "Type" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_${dir}" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $group
set_property -dict [list \
"widget" "comboBox" \
"display_name" "AXI Protocol" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_${dir}" -component $cc]
ipgui::move_param -component $cc -order 2 $p -parent $group
set_property -dict [list \
"display_name" "Bus Width" \
axi_dmac: Allow wider FIFO/AXI Stream interface On large projects with multiple channels the databus on the FIFO/AXI stream interface can get wider that 1024 bits. This commit allows a wider range for all the interfaces, in case for the memory mapped interfaces where the range is 32-1024 the user selects a bus width out of range that will be handled by the IPI.
2021-02-19 08:11:34 +00:00
"tooltip" "Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits" \
axi_dmac: Beautify IPI GUI Group the axi_dmac parameters by function and provide a human readable name for the IPI GUI. This makes it easier to understand what parameter does what when using the IPI GUI to configure the core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:58:32 +00:00
] $p
set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc]
ipgui::move_param -component $cc -order 3 $p -parent $group
set_property -dict [list \
"display_name" "Insert Register Slice" \
] $p
}
set p [ipgui::get_guiparamspec -name "SYNC_TRANSFER_START" -component $cc]
ipgui::move_param -component $cc -order 4 $p -parent $src_group
set_property -dict [list \
"display_name" "Transfer Start Synchronization Support" \
] $p
axi_dmac: Add parameter controlling AWCACHE On architectures with ports that support cache coherency, the AWCACHE signal must be set to indicate that transactions are cached. This patch adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
2022-05-05 08:35:34 +00:00
set p [ipgui::get_guiparamspec -name "CACHE_COHERENT_DEST" -component $cc]
ipgui::move_param -component $cc -order 4 $p -parent $dest_group
set_property -dict [list \
"tooltip" "Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)" \
] $p
set_property -dict [list \
"display_name" "Assume cache coherent" \
"enablement_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
"value_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
"enablement_value" "false" \
] [ipx::get_user_parameters CACHE_COHERENT_DEST -of_objects $cc]
axi_dmac: Beautify IPI GUI Group the axi_dmac parameters by function and provide a human readable name for the IPI GUI. This makes it easier to understand what parameter does what when using the IPI GUI to configure the core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:58:32 +00:00
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
-parent $page0 -display_name "General Configuration"]
set p [ipgui::get_guiparamspec -name "ID" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $general_group
set_property -dict [list \
"display_name" "Core ID" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_LENGTH_WIDTH" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $general_group
set_property -dict [list \
"display_name" "DMA Transfer Length Register Width" \
] $p
set p [ipgui::get_guiparamspec -name "FIFO_SIZE" -component $cc]
ipgui::move_param -component $cc -order 2 $p -parent $general_group
set_property -dict [list \
axi_dmac: List valid store-and-forward memory sizes For correct operation the store-and-forward memory size must be a power-of-two in the range of 2 to 32. This is simple enough so we can list all values and let the IP Integrator and QSYS perform proper validation of the parameter. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-30 07:27:59 +00:00
"widget" "comboBox" \
axi_dmac: Use a more descriptive label for the store-and-forward memory size The label for the store-and-forward memory size configuration option at the moment is just "FIFO Size" and while the store-and-forward memory uses a FIFO that is just a implementation detail. Change the label to "Store-and-Forward Memory Size". This is more descriptive as it references the function not the implementation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-30 07:32:38 +00:00
"display_name" "Store-and-Forward Memory Size (In Bursts)" \
axi_dmac: Beautify IPI GUI Group the axi_dmac parameters by function and provide a human readable name for the IPI GUI. This makes it easier to understand what parameter does what when using the IPI GUI to configure the core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:58:32 +00:00
] $p
set p [ipgui::get_guiparamspec -name "MAX_BYTES_PER_BURST" -component $cc]
ipgui::move_param -component $cc -order 3 $p -parent $general_group
set_property -dict [list \
"display_name" "Maximum Bytes per Burst" \
] $p
set feature_group [ipgui::add_group -name "Features" -component $cc \
-parent $page0 -display_name "Features"]
set p [ipgui::get_guiparamspec -name "CYCLIC" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $feature_group
set_property -dict [list \
"display_name" "Cyclic Transfer Support" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $feature_group
set_property -dict [list \
"display_name" "2D Transfer Support" \
] $p
set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
-parent $page0 -display_name {Clock Domain Configuration}]
set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SRC" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $clk_group
set_property -dict [list \
"display_name" "Request and Source Clock Asynchronous" \
] $p
set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_DEST" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $clk_group
set_property -dict [list \
"display_name" "Source and Destination Clock Asynchronous" \
] $p
set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_REQ" -component $cc]
ipgui::move_param -component $cc -order 2 $p -parent $clk_group
set_property -dict [list \
"display_name" "Destination and Request Clock Asynchronous" \
] $p
axi_dmac: Make debug register optional The debug registers are useful during development but are rarely used in a production design. Add a option that allows to disable them, this reduces the resource utilization of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 14:00:51 +00:00
set dbg_group [ipgui::add_group -name {Debug} -component $cc \
-parent $page0 -display_name {Debug}]
set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $dbg_group
set_property -dict [list \
"display_name" "Disable Debug Registers" \
] $p
axi_dmac: diagnostic interface in bursts This change adds a diagnostic interface to the DMAC core. The interface exposes internal information about the core, information which can't be exposed through AXI registers due the latency and update rate. Such information is the fullness of the internal buffer. For this is exposed in bursts and is driven from the destination clock domain, as this is reflected in its name. The signal has a fixed size and is dimensioned by taking in account the supported maximum number of bursts of 128.
2018-06-07 13:20:27 +00:00
set p [ipgui::get_guiparamspec -name "ENABLE_DIAGNOSTICS_IF" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $dbg_group
set_property -dict [list \
"display_name" "Enable Diagnostics Interface" \
] $p
axi_dmac: Configure AXI address width according to the mapped address space Currently the AXI address width of the DMA is always 32-bit. But not all address spaces are so large that they require 32-bit to address all memory. Extract the size of the address space that the DMA is connected too and configure reduce the address size to the minimum required to address the full address space. This slightly reduces utilization. If no mapped address space can be found the default of 32 bits is used for the address. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-06 07:30:22 +00:00
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc]
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc]
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc]
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc]
axi_dmac: bundle AXI Stream signals into bus for Intel Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.
2019-05-13 11:35:55 +00:00
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc]
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc]
axi_dmac: Configure AXI address width according to the mapped address space Currently the AXI address width of the DMA is always 32-bit. But not all address spaces are so large that they require 32-bit to address all memory. Extract the size of the address space that the DMA is connected too and configure reduce the address size to the minimum required to address the full address space. This slightly reduces utilization. If no mapped address space can be found the default of 32 bits is used for the address. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-06 07:30:22 +00:00
axi_dmac: Beautify IPI GUI Group the axi_dmac parameters by function and provide a human readable name for the IPI GUI. This makes it easier to understand what parameter does what when using the IPI GUI to configure the core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:58:32 +00:00
ipx::create_xgui_files [ipx::current_core]
axi_dmac: Add validation values to IPI package Add validation values for the different configuration parameters. This enables the tools to check whether the configured value is valid and avoids accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 13:53:54 +00:00
ipx::save_core $cc