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pluto_hdl_adi/library/spi_engine/axi_spi_engine/Makefile

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Add SPI Engine framework SPI Engine is a highly flexible and powerful SPI controller framework. It consist out of multiple sub-modules which communicate over well defined interfaces. This allows a high degree of flexibility and re-usability while at the same time staying highly customizable and easily extensible. Currently included are four components: * SPI Engine execution module: The excution module is responsible for handling the low-level physical interface SPI logic. * SPI Engine AXI interface module: The AXI interface module allows memory mapped acccess to a SPI bus control stream and can be used to implement a software driver that controls the SPI bus. * SPI Engine offload module: The offload module allows to store a predefined SPI Engine command and data stream which will be send out when a external trigger signal is asserted. * SPI Engine interconnect module: The interconnect module allows to combine multiple control streams into a single stream giving multiple control modules access to a execution module. For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 10:12:11 +00:00
####################################################################################
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
Add SPI Engine framework SPI Engine is a highly flexible and powerful SPI controller framework. It consist out of multiple sub-modules which communicate over well defined interfaces. This allows a high degree of flexibility and re-usability while at the same time staying highly customizable and easily extensible. Currently included are four components: * SPI Engine execution module: The excution module is responsible for handling the low-level physical interface SPI logic. * SPI Engine AXI interface module: The AXI interface module allows memory mapped acccess to a SPI bus control stream and can be used to implement a software driver that controls the SPI bus. * SPI Engine offload module: The offload module allows to store a predefined SPI Engine command and data stream which will be send out when a external trigger signal is asserted. * SPI Engine interconnect module: The interconnect module allows to combine multiple control streams into a single stream giving multiple control modules access to a execution module. For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 10:12:11 +00:00
## Auto-generated, do not modify!
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
LIBRARY_NAME := axi_spi_engine
Add SPI Engine framework SPI Engine is a highly flexible and powerful SPI controller framework. It consist out of multiple sub-modules which communicate over well defined interfaces. This allows a high degree of flexibility and re-usability while at the same time staying highly customizable and easily extensible. Currently included are four components: * SPI Engine execution module: The excution module is responsible for handling the low-level physical interface SPI logic. * SPI Engine AXI interface module: The AXI interface module allows memory mapped acccess to a SPI bus control stream and can be used to implement a software driver that controls the SPI bus. * SPI Engine offload module: The offload module allows to store a predefined SPI Engine command and data stream which will be send out when a external trigger signal is asserted. * SPI Engine interconnect module: The interconnect module allows to combine multiple control streams into a single stream giving multiple control modules access to a execution module. For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 10:12:11 +00:00
makefile: Regenerate make files
2020-10-14 08:32:43 +00:00
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += axi_spi_engine.v
updated makefiles
2016-12-09 21:06:41 +00:00
spi_engine: Update util_axis_fifo instances
2020-11-18 16:15:21 +00:00
XILINX_DEPS += ../../common/ad_rst.v
XILINX_DEPS += ../../common/up_axi.v
makefile: Update makefiles
2020-04-29 10:30:01 +00:00
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
Makefile: Update makefiles
2019-08-22 09:00:05 +00:00
XILINX_DEPS += axi_spi_engine_constr.ttcl
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
XILINX_DEPS += axi_spi_engine_ip.tcl
updated makefiles
2016-12-09 21:06:41 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc
Add SPI Engine framework SPI Engine is a highly flexible and powerful SPI controller framework. It consist out of multiple sub-modules which communicate over well defined interfaces. This allows a high degree of flexibility and re-usability while at the same time staying highly customizable and easily extensible. Currently included are four components: * SPI Engine execution module: The excution module is responsible for handling the low-level physical interface SPI logic. * SPI Engine AXI interface module: The AXI interface module allows memory mapped acccess to a SPI bus control stream and can be used to implement a software driver that controls the SPI bus. * SPI Engine offload module: The offload module allows to store a predefined SPI Engine command and data stream which will be send out when a external trigger signal is asserted. * SPI Engine interconnect module: The interconnect module allows to combine multiple control streams into a single stream giving multiple control modules access to a execution module. For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 10:12:11 +00:00
makefile: Regenerate make files
2020-10-14 08:32:43 +00:00
INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
axi_spi_engine: Fix util_axis_fifo instance related issues
2020-12-14 15:19:12 +00:00
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
makefile: Regenerate make files
2020-10-14 08:32:43 +00:00
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_gray.v
INTEL_DEPS += axi_spi_engine_constr.sdc
INTEL_DEPS += axi_spi_engine_hw.tcl
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
include ../../scripts/library.mk