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pluto_hdl_adi/projects/ad4134_fmc/zed/system_bd.tcl

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projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-05-06 13:08:39 +00:00
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
source ../common/ad4134_bd.tcl