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pluto_hdl_adi/library/spi_engine/scripts/spi_engine.tcl

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SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} {
puts "echo_sclk: $echo_sclk"
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
create_bd_cell -type hier $name
current_bd_instance /$name
if {$async_spi_clk == 1} {
create_bd_pin -dir I -type clk spi_clk
}
spi_engine_execution: Add echoed SCLK support There are boards (e.g. AD4630-24) which take the SCLK and echo back to the FPGA through a level shifter - doing this removes the effect of round-trip timing delays from the level shifter. This is commonly done whenever isolators are used since they are very slow. By setting the ECHO_SCLK parameter to 1, the IP will use the incoming echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still synchronous to the SPI clock, and it's generated after the last valid SDI latch. The designer's responsibility is to time the SDI shift registers in order to respect the design requirements.
2020-07-22 12:45:27 +00:00
if {$echo_sclk == 1} {
create_bd_pin -dir I -type clk echo_sclk
}
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
create_bd_pin -dir I -type clk clk
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir I trigger
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
set execution "${name}_execution"
set axi_regmap "${name}_axi_regmap"
set offload "${name}_offload"
set interconnect "${name}_interconnect"
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_ip_instance spi_engine_execution $execution
ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi
ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1
ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay
ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_ip_instance axi_spi_engine $axi_regmap
ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_ip_instance spi_engine_offload $offload
ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK $async_spi_clk
ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_ip_instance spi_engine_interconnect $interconnect
ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
ad_connect $interconnect/m_ctrl $execution/ctrl
ad_connect $offload/offload_sdi m_axis_sample
ad_connect $offload/trigger trigger
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect $execution/spi m_spi
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect clk $axi_regmap/s_axi_aclk
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
if {$async_spi_clk == 1} {
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect spi_clk $offload/spi_clk
ad_connect spi_clk $offload/ctrl_clk
ad_connect spi_clk $execution/clk
ad_connect spi_clk $axi_regmap/spi_clk
ad_connect spi_clk $interconnect/clk
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
} else {
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect clk $offload/spi_clk
ad_connect clk $offload/ctrl_clk
ad_connect clk $execution/clk
ad_connect clk $axi_regmap/spi_clk
ad_connect clk $interconnect/clk
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
}
spi_engine_execution: Add echoed SCLK support There are boards (e.g. AD4630-24) which take the SCLK and echo back to the FPGA through a level shifter - doing this removes the effect of round-trip timing delays from the level shifter. This is commonly done whenever isolators are used since they are very slow. By setting the ECHO_SCLK parameter to 1, the IP will use the incoming echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still synchronous to the SPI clock, and it's generated after the last valid SDI latch. The designer's responsibility is to time the SDI shift registers in order to respect the design requirements.
2020-07-22 12:45:27 +00:00
if {$echo_sclk == 1} {
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect echo_sclk $execution/echo_sclk
spi_engine_execution: Add echoed SCLK support There are boards (e.g. AD4630-24) which take the SCLK and echo back to the FPGA through a level shifter - doing this removes the effect of round-trip timing delays from the level shifter. This is commonly done whenever isolators are used since they are very slow. By setting the ECHO_SCLK parameter to 1, the IP will use the incoming echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still synchronous to the SPI clock, and it's generated after the last valid SDI latch. The designer's responsibility is to time the SDI shift registers in order to respect the design requirements.
2020-07-22 12:45:27 +00:00
}
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
ad_connect $axi_regmap/spi_resetn $execution/resetn
ad_connect $axi_regmap/spi_resetn $interconnect/resetn
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect resetn $axi_regmap/s_axi_aresetn
ad_connect irq $axi_regmap/irq
spi_engine: Add spi_engine.tcl
2020-09-24 10:54:39 +00:00
current_bd_instance /
}