pluto_hdl_adi/library/axi_dmac/splitter.v

// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// The user should read each of these license terms, and understand the
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module splitter #(

  parameter NUM_M = 2
) (
  input clk,
  input resetn,

  input s_valid,
  output s_ready,

  output [NUM_M-1:0] m_valid,
  input [NUM_M-1:0] m_ready
);

  reg [NUM_M-1:0] acked;

  assign s_ready = &(m_ready | acked);
  assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};

  always @(posedge clk) begin
    if (resetn == 1'b0) begin
      acked <= {NUM_M{1'b0}};
    end else begin
      if (s_valid & s_ready)
        acked <= {NUM_M{1'b0}};
      else
        acked <= acked | (m_ready & m_valid);
    end
  end

endmodule