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pluto_hdl_adi/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcjesdac1: Convert to ADI JESD204 Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:52:43 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# adc peripherals
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
ad_ip_instance axi_adxcvr axi_ad9250_xcvr
ad_ip_parameter axi_ad9250_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9250_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9250_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad9250_xcvr CONFIG.LPM_OR_DFE_N 0
fmcjesdadc1: Fix OUT_CLK_SEL configuration The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as binary numbers. But the tools will interpret them as decimal number resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter values as decimal values to avoid this. This is not a critical issue since software will overwrite this setting at system boot-up. But it should be fixed anyway. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:07:28 +00:00
ad_ip_parameter axi_ad9250_xcvr CONFIG.OUT_CLK_SEL 0x2
ad_ip_parameter axi_ad9250_xcvr CONFIG.SYS_CLK_SEL 0x0
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
fmcjesdac1: Convert to ADI JESD204 Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:52:43 +00:00
adi_axi_jesd204_rx_create axi_ad9250_jesd 4
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
ad_ip_instance util_bsplit data_bsplit
ad_ip_parameter data_bsplit CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter data_bsplit CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_ad9250 axi_ad9250_0_core
ad_ip_instance axi_ad9250 axi_ad9250_1_core
fmcjesdadc1: Use new pack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:06:02 +00:00
ad_ip_instance util_cpack2 axi_ad9250_0_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance util_cpack2 axi_ad9250_1_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
ad_ip_instance axi_dmac axi_ad9250_0_dma
ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9250_0_dma CONFIG.ID 0
ad_ip_parameter axi_ad9250_0_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9250_0_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9250_0_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9250_0_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_DATA_WIDTH_DEST 64
fmcjesdadc1: increase DMAC FIFO size The DMAC FIFO ocasionally overflow, increased it's size to give more time the MM interface to move out the data.
2018-05-23 12:05:16 +00:00
ad_ip_parameter axi_ad9250_0_dma CONFIG.FIFO_SIZE 8
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
ad_ip_instance axi_dmac axi_ad9250_1_dma
ad_ip_parameter axi_ad9250_1_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9250_1_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9250_1_dma CONFIG.ID 0
ad_ip_parameter axi_ad9250_1_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9250_1_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9250_1_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9250_1_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9250_1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9250_1_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9250_1_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9250_1_dma CONFIG.DMA_DATA_WIDTH_DEST 64
fmcjesdadc1: increase DMAC FIFO size The DMAC FIFO ocasionally overflow, increased it's size to give more time the MM interface to move out the data.
2018-05-23 12:05:16 +00:00
ad_ip_parameter axi_ad9250_0_dma CONFIG.FIFO_SIZE 8
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
# transceiver core
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
ad_ip_instance util_adxcvr util_fmcjesdadc1_xcvr
util_adxcvr: Fix parameter setup at instantiation If a parameter value is defined as a string binary (e.g. "001001000000"), it can confuse the tool, and the value may be used as a decimal number. To prevent this issue and to improve readability converting all the binary constants into hexadecimal.
2017-04-27 12:35:39 +00:00
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.QPLL_FBDIV 0x80
fmcjesdadc1: Update IP instantiations
2017-04-21 12:08:16 +00:00
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.RX_PMA_CFG 0x00018480
ad_ip_parameter util_fmcjesdadc1_xcvr CONFIG.RX_CDR_CFG 0x03000023ff10200020
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
# reference clocks & resets
create_bd_port -dir I rx_ref_clk_0
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_*
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
create_bd_port -dir O rx_core_clk
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
# connections (adc)
fmcjesdadc1: Updated project to 2015.2.1 - updated to the new jesd framework - added cpack core
2015-09-24 16:12:40 +00:00
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 rx_core_clk
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
fmcjesdac1: Convert to ADI JESD204 Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:52:43 +00:00
ad_connect axi_ad9250_jesd/rx_data_tdata data_bsplit/data
fmcjesdadc1: Use new pack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:06:02 +00:00
for {set i 0} {$i < 2} {incr i} {
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_${i}_core/rx_clk
ad_connect axi_ad9250_jesd/rx_sof axi_ad9250_${i}_core/rx_sof
ad_connect axi_ad9250_${i}_core/rx_data data_bsplit/split_data_${i}
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_${i}_cpack/clk
ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_${i}_cpack/reset
ad_connect axi_ad9250_${i}_core/adc_dovf axi_ad9250_${i}_cpack/fifo_wr_overflow
ad_connect axi_ad9250_${i}_core/adc_valid_a axi_ad9250_${i}_cpack/fifo_wr_en
ad_connect axi_ad9250_${i}_core/adc_enable_a axi_ad9250_${i}_cpack/enable_0
ad_connect axi_ad9250_${i}_core/adc_data_a axi_ad9250_${i}_cpack/fifo_wr_data_0
ad_connect axi_ad9250_${i}_core/adc_enable_b axi_ad9250_${i}_cpack/enable_1
ad_connect axi_ad9250_${i}_core/adc_data_b axi_ad9250_${i}_cpack/fifo_wr_data_1
ad_connect axi_ad9250_${i}_core/adc_clk axi_ad9250_${i}_dma/fifo_wr_clk
ad_connect axi_ad9250_${i}_dma/fifo_wr axi_ad9250_${i}_cpack/packed_fifo_wr
}
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9250_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core
ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core
fmcjesdac1: Convert to ADI JESD204 Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:52:43 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad9250_jesd
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma
ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma
# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9250_xcvr/m_axi
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
# interconnect (adc)
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9250_0_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9250_1_dma/m_dest_axi
fmcjesdadc1: Update projects to xcvr framework This commit contains modifications for Xilinx only
2016-11-10 08:59:52 +00:00
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_connect sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn
#interrupts
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-11 mb-14 axi_ad9250_jesd/irq
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interrupt ps-12 mb-12 axi_ad9250_1_dma/irq
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-13 mb-13 axi_ad9250_0_dma/irq
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00