158 lines
7.1 KiB
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158 lines
7.1 KiB
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.. _releases:
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Releases
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===============================================================================
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The HDL is released as git branches bi-annually. The release branches
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are created first and then tested before being made official. That is,
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the existence of a branch does not mean it is a fully tested release.
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Also, the release branch is tested **only** on certain versions of the tools
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and may **not** work with other versions of the tools.
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The projects that are tested and supported in a release branch are listed
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along with the ADI library cores that are used.
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The release branch may contain other projects that are in development;
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one must assume these are **not** tested, therefore **not** supported by
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this release.
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Porting a release branch to another Tool version
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-------------------------------------------------------------------------------
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It is possible to port a release branch to another tool version, though
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not recommended. The ADI libraries should work across different versions
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of the tools, but the projects may not. The issues are most likely with
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the Intel and AMD Xilinx cores. If you must still do this, note the
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following:
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First, disable the version check of the scripts.
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The ADI build scripts are making sure that the releases are being run on
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the validated tool version. It will promptly notify the user if he or
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she trying to use an unsupported version of tools. You need to disable
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this check by setting the environment variable ``ADI_IGNORE_VERSION_CHECK``.
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Second, make Intel and AMD IP cores version change.
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The Intel projects should automatically be changed by Quartus. The
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Vivado projects are a bit tricky. The GUI automatically updates the
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cores, but the **Tcl flow does not**.
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Thus, it may be easier to create the project file with the supported version
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first, then opening it with the new version.
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After which, update the Tcl scripts accordingly.
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The versions are specified in the following format.
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.. code-block:: tcl
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:linenos:
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add_instance sys_cpu altera_nios2_gen2 16.0
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set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb]
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You should now be able to build the design and test things out. In most
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cases, it should work without much effort. If it doesn't, do an
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incremental update and debug accordingly.
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Release branches
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - Releases
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- Intel
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- AMD Xilinx
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- Release notes
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- List of supported projects and IP cores
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* - :git-hdl:`master`
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- Quartus Pro 23.2
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- Vivado 2023.1
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-
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-
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* - :git-hdl:`hdl_2021_r2 <hdl_2021_r2:>`
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- Quartus Pro 21.4
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- Vivado 2021.2
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- `Release notes 2021_R2 <https://github.com/analogdevicesinc/hdl/releases/tag/2021_R2>`_
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- `Wiki list for hdl_2021_r2 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2021_r2>`_
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* - :git-hdl:`hdl_2021_r1 <hdl_2021_r1:>`
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- Quartus Pro 21.2
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- Vivado 2021.1
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- `Release notes 2021_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2021_R1>`_
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- `Wiki list for hdl_2021_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2021_r1>`_
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* - :git-hdl:`hdl_2019_r2 <hdl_2019_r2:>`
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- Quartus Pro 19.3
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- Vivado 2019.1
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- `Release notes 2019_R2 <https://github.com/analogdevicesinc/hdl/releases/tag/2019_R2>`_
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- `Wiki list for hdl_2019_r2 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2019_r2>`_
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* - :git-hdl:`hdl_2019_r1 <hdl_2019_r1:>`
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- Quartus Pro 18.1
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- Vivado 2018.3
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- `Release notes 2019_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2019_R1>`_
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- `Wiki list for hdl_2019_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2019_r1>`_
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* - :git-hdl:`hdl_2018_r2 <hdl_2018_r2:>`
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- Quartus Pro 18.0
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- Vivado 2018.2
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- `Release notes 2018_R2 <https://github.com/analogdevicesinc/hdl/releases/tag/2018_R2>`_
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- `Wiki list for hdl_2018_r2 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2018_r2>`_
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* - :git-hdl:`hdl_2018_r1 <hdl_2018_r1:>`
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- Quartus Pro 17.1.1
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- Vivado 2017.4.1
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- `Release notes 2018_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2018_R1>`_
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- `Wiki list for hdl_2018_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2018_r1>`_
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* - :git-hdl:`hdl_2017_r1 <hdl_2017_r1:>`
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- Quartus Pro 16.1
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- Vivado 2016.4
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- `Release notes 2017_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2017_R1>`_
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- `Wiki list for hdl_2017_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2017_r1>`_
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* - :git-hdl:`hdl_2016_r2 <hdl_2016_r2:>`
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- Quartus Pro 16.0
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- Vivado 2016.2
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- `Release notes 2016_R2 <https://github.com/analogdevicesinc/hdl/releases/tag/2016_R2>`_
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- `Wiki list for hdl_2016_r2 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2016_r2>`_
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* - :git-hdl:`hdl_2016_r1 <hdl_2016_r1:>`
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- Quartus Pro 15.1
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- Vivado 2015.4.2
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- `Release notes 2016_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2016_R1>`_
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- `Wiki list for hdl_2016_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2016_r1>`_
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* - :git-hdl:`hdl_2015_r2 <hdl_2015_r2:>`
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- Quartus Pro 15.0.2
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- Vivado 2015.2
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- `Release notes 2015_R2 <https://github.com/analogdevicesinc/hdl/releases/tag/2015_R2>`_
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- `Wiki list for hdl_2015_r2 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2015_r2>`_
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* - :git-hdl:`hdl_2015_r1 <hdl_2015_r1:>`
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- Quartus Pro 14.1
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- Vivado 2014.4.1
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- `Release notes 2015_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2015_R1>`_
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- `Wiki list for hdl_2015_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2015_r1>`_
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* - :git-hdl:`hdl_2014_r2 <hdl_2014_r2:>`
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- Quartus Pro 14.0
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- Vivado 2014.2
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- `Release notes 2014_R2 <https://github.com/analogdevicesinc/hdl/releases/tag/2014_R2>`_
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- `Wiki list for hdl_2014_r2 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2014_r2>`_
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* - :git-hdl:`hdl_2014_r1 <hdl_2014_r1:>`
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- Quartus Pro 14.0
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- Vivado 2013.4
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- `Release notes 2014_R1 <https://github.com/analogdevicesinc/hdl/releases/tag/2014_R1>`_
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- `Wiki list for hdl_2014_r1 <https://wiki.analog.com/resources/fpga/docs/hdl/downloads_2014_r1>`_
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About the tools we use
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-------------------------------------------------------------------------------
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When Intel or AMD have a new release, we usually follow them and update our
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tools in a timely manner.
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Changing the version of tool used on a branch is done by updating the
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git-hdl:`adi_env.tcl <master:scripts/adi_env.tcl>` script.
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If the tool version is not the one you want to use, keep in mind that when
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making a setup, you will have to build the software files with the same
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version, otherwise you might encounter problems in your setup.
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For example, you want to use an older version of Vivado on the master branch
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which uses a newer one. Then you will need to manually build the software
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files from the master branch, with the same version of Vitis too. Or for
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Linux, to use the proper version of CROSS_COMPILE, etc.
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