175 lines
5.9 KiB
Tcl
175 lines
5.9 KiB
Tcl
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set top_design [current_bd_design]
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create_bd_design "jesd_phy"
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create_bd_cell -type ip -vlnv xilinx.com:ip:gt_bridge_ip:1.1 gt_bridge_ip_0
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set_property -dict [list \
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CONFIG.BYPASS_MODE {true} \
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CONFIG.IP_PRESET {GTY-JESD204_64B66B} \
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CONFIG.IP_LR0_SETTINGS { \
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PRESET GTY-JESD204_64B66B \
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INTERNAL_PRESET JESD204_64B66B \
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GT_TYPE GTY \
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GT_DIRECTION DUPLEX \
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TX_LINE_RATE 24.75 \
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TX_PLL_TYPE LCPLL \
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TX_REFCLK_FREQUENCY 375 \
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TX_ACTUAL_REFCLK_FREQUENCY 375.000000000000 \
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TX_FRACN_ENABLED true \
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TX_FRACN_NUMERATOR 0 \
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TX_REFCLK_SOURCE R0 \
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TX_DATA_ENCODING 64B66B_ASYNC \
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TX_USER_DATA_WIDTH 64 \
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TX_INT_DATA_WIDTH 64 \
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TX_BUFFER_MODE 1 \
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TX_BUFFER_BYPASS_MODE Fast_Sync \
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TX_PIPM_ENABLE false \
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TX_OUTCLK_SOURCE TXPROGDIVCLK \
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TXPROGDIV_FREQ_ENABLE true \
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TXPROGDIV_FREQ_SOURCE LCPLL \
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TXPROGDIV_FREQ_VAL 375.000 \
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TX_DIFF_SWING_EMPH_MODE CUSTOM \
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TX_64B66B_SCRAMBLER false \
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TX_64B66B_ENCODER false \
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TX_64B66B_CRC false \
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TX_RATE_GROUP A \
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RX_LINE_RATE 24.75 \
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RX_PLL_TYPE LCPLL \
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RX_REFCLK_FREQUENCY 375 \
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RX_ACTUAL_REFCLK_FREQUENCY 375.000000000000 \
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RX_FRACN_ENABLED true \
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RX_FRACN_NUMERATOR 0 \
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RX_REFCLK_SOURCE R0 \
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RX_DATA_DECODING 64B66B_ASYNC \
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RX_USER_DATA_WIDTH 64 \
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RX_INT_DATA_WIDTH 64 \
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RX_BUFFER_MODE 1 \
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RX_OUTCLK_SOURCE RXPROGDIVCLK \
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RXPROGDIV_FREQ_ENABLE true \
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RXPROGDIV_FREQ_SOURCE LCPLL \
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RXPROGDIV_FREQ_VAL 375.000 \
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INS_LOSS_NYQ 12 \
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RX_EQ_MODE LPM \
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RX_COUPLING AC \
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RX_TERMINATION PROGRAMMABLE \
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RX_RATE_GROUP A \
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RX_TERMINATION_PROG_VALUE 800 \
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RX_PPM_OFFSET 0 \
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RX_64B66B_DESCRAMBLER false \
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RX_64B66B_DECODER false \
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RX_64B66B_CRC false \
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OOB_ENABLE false \
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RX_COMMA_ALIGN_WORD 1 \
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RX_COMMA_SHOW_REALIGN_ENABLE true \
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PCIE_ENABLE false \
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RX_COMMA_P_ENABLE false \
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RX_COMMA_M_ENABLE false \
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RX_COMMA_DOUBLE_ENABLE false \
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RX_COMMA_P_VAL 0101111100 \
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RX_COMMA_M_VAL 1010000011 \
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RX_COMMA_MASK 0000000000 \
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RX_SLIDE_MODE OFF \
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RX_SSC_PPM 0 \
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RX_CB_NUM_SEQ 0 \
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RX_CB_LEN_SEQ 1 \
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RX_CB_MAX_SKEW 1 \
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RX_CB_MAX_LEVEL 1 \
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RX_CB_MASK_0_0 false \
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RX_CB_VAL_0_0 00000000 \
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RX_CB_K_0_0 false \
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RX_CB_DISP_0_0 false \
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RX_CB_MASK_0_1 false \
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RX_CB_VAL_0_1 00000000 \
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RX_CB_K_0_1 false \
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RX_CB_DISP_0_1 false \
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RX_CB_MASK_0_2 false \
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RX_CB_VAL_0_2 00000000 \
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RX_CB_K_0_2 false \
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RX_CB_DISP_0_2 false \
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RX_CB_MASK_0_3 false \
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RX_CB_VAL_0_3 00000000 \
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RX_CB_K_0_3 false \
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RX_CB_DISP_0_3 false \
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RX_CB_MASK_1_0 false \
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RX_CB_VAL_1_0 00000000 \
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RX_CB_K_1_0 false \
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RX_CB_DISP_1_0 false \
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RX_CB_MASK_1_1 false \
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RX_CB_VAL_1_1 00000000 \
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RX_CB_K_1_1 false \
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RX_CB_DISP_1_1 false \
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RX_CB_MASK_1_2 false \
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RX_CB_VAL_1_2 00000000 \
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RX_CB_K_1_2 false \
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RX_CB_DISP_1_2 false \
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RX_CB_MASK_1_3 false \
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RX_CB_VAL_1_3 00000000 \
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RX_CB_K_1_3 false \
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RX_CB_DISP_1_3 false \
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RX_CC_NUM_SEQ 0 \
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RX_CC_LEN_SEQ 1 \
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RX_CC_PERIODICITY 5000 \
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RX_CC_KEEP_IDLE DISABLE \
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RX_CC_PRECEDENCE ENABLE \
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RX_CC_REPEAT_WAIT 0 \
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RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \
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RX_CC_MASK_0_0 false \
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RX_CC_VAL_0_0 00000000 \
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RX_CC_K_0_0 false \
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RX_CC_DISP_0_0 false \
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RX_CC_MASK_0_1 false \
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RX_CC_VAL_0_1 00000000 \
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RX_CC_K_0_1 false \
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RX_CC_DISP_0_1 false \
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RX_CC_MASK_0_2 false \
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RX_CC_VAL_0_2 00000000 \
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RX_CC_K_0_2 false \
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RX_CC_DISP_0_2 false \
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RX_CC_MASK_0_3 false \
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RX_CC_VAL_0_3 00000000 \
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RX_CC_K_0_3 false \
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RX_CC_DISP_0_3 false \
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RX_CC_MASK_1_0 false \
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RX_CC_VAL_1_0 00000000 \
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RX_CC_K_1_0 false \
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RX_CC_DISP_1_0 false \
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RX_CC_MASK_1_1 false \
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RX_CC_VAL_1_1 00000000 \
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RX_CC_K_1_1 false \
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RX_CC_DISP_1_1 false \
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RX_CC_MASK_1_2 false \
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RX_CC_VAL_1_2 00000000 \
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RX_CC_K_1_2 false \
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RX_CC_DISP_1_2 false \
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RX_CC_MASK_1_3 false \
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RX_CC_VAL_1_3 00000000 \
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RX_CC_K_1_3 false \
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RX_CC_DISP_1_3 false \
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PCIE_USERCLK2_FREQ 250 \
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PCIE_USERCLK_FREQ 250 \
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RX_JTOL_FC 10 \
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RX_JTOL_LF_SLOPE -20 \
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RX_BUFFER_BYPASS_MODE Fast_Sync \
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RX_BUFFER_BYPASS_MODE_LANE MULTI \
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RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \
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RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \
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RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
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TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
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RESET_SEQUENCE_INTERVAL 0 \
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RX_COMMA_PRESET NONE \
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RX_COMMA_VALID_ONLY 0 \
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} \
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] [get_bd_cells gt_bridge_ip_0]
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apply_bd_automation -rule xilinx.com:bd_rule:gt_ips -config { DataPath_Interface_Connection {Auto} Lane0_selection {NULL} Lane10_selection {NULL} Lane11_selection {NULL} Lane12_selection {NULL} Lane13_selection {NULL} Lane14_selection {NULL} Lane15_selection {NULL} Lane16_selection {NULL} Lane17_selection {NULL} Lane18_selection {NULL} Lane19_selection {NULL} Lane1_selection {NULL} Lane2_selection {NULL} Lane3_selection {NULL} Lane4_selection {NULL} Lane5_selection {NULL} Lane6_selection {NULL} Lane7_selection {NULL} Lane8_selection {NULL} Lane9_selection {NULL} Quad0_selection {NULL} Quad10_selection {NULL} Quad11_selection {NULL} Quad12_selection {NULL} Quad13_selection {NULL} Quad14_selection {NULL} Quad15_selection {NULL} Quad16_selection {NULL} Quad17_selection {NULL} Quad18_selection {NULL} Quad19_selection {NULL} Quad1_selection {NULL} Quad2_selection {NULL} Quad3_selection {NULL} Quad4_selection {NULL} Quad5_selection {NULL} Quad6_selection {NULL} Quad7_selection {NULL} Quad8_selection {NULL} Quad9_selection {NULL}} [get_bd_cells gt_bridge_ip_0]
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validate_bd_design
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save_bd_design
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close_bd_design [current_bd_design]
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current_bd_design [get_bd_designs $top_design]
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