375 lines
13 KiB
Coq
375 lines
13 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// hps-ddr4 (32)
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input hps_ddr_ref_clk,
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output [ 0:0] hps_ddr_clk_p,
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output [ 0:0] hps_ddr_clk_n,
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output [ 16:0] hps_ddr_a,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_reset_n,
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output [ 0:0] hps_ddr_act_n,
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output [ 0:0] hps_ddr_par,
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input [ 0:0] hps_ddr_alert_n,
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inout [ 3:0] hps_ddr_dqs_p,
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inout [ 3:0] hps_ddr_dqs_n,
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inout [ 31:0] hps_ddr_dq,
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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input [ 0:0] hps_eth_rxctl,
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input [ 3:0] hps_eth_rxd,
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output [ 0:0] hps_eth_txclk,
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output [ 0:0] hps_eth_txctl,
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output [ 3:0] hps_eth_txd,
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output [ 0:0] hps_eth_mdc,
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inout [ 0:0] hps_eth_mdio,
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// hps-sdio
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output [ 0:0] hps_sdio_clk,
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inout [ 0:0] hps_sdio_cmd,
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inout [ 7:0] hps_sdio_d,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
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input [ 0:0] hps_usb_nxt,
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output [ 0:0] hps_usb_stp,
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inout [ 7:0] hps_usb_d,
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// hps-uart
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input [ 0:0] hps_uart_rx,
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output [ 0:0] hps_uart_tx,
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// hps-i2c (shared w fmc-a, fmc-b)
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inout [ 0:0] hps_i2c_sda,
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inout [ 0:0] hps_i2c_scl,
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// hps-gpio (max-v-u16)
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inout [ 3:0] hps_gpio,
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// gpio (max-v-u21)
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input [ 7:0] gpio_bd_i,
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output [ 3:0] gpio_bd_o,
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// adrv9001-interface
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output spi_clk,
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output spi_dio,
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input spi_do,
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output spi_en,
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input fpga_ref_clk_n,
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input fpga_ref_clk_p,
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// Device clock passed through 9001
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input dev_clk_in,
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input fpga_mcs_in_n,
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input fpga_mcs_in_p,
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output dev_mcs_fpga_out_n,
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output dev_mcs_fpga_out_p,
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inout dgpio_0,
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inout dgpio_1,
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inout dgpio_2,
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inout dgpio_3,
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inout dgpio_4,
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inout dgpio_5,
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inout dgpio_6,
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inout dgpio_7,
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inout dgpio_8,
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inout dgpio_9,
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inout dgpio_10,
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inout dgpio_11,
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inout gp_int,
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inout mode,
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inout reset_trx,
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// physical interface
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input rx1_dclk_in_n,
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input rx1_dclk_in_p,
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output rx1_enable,
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input rx1_idata_in_n,
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input rx1_idata_in_p,
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input rx1_qdata_in_n,
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input rx1_qdata_in_p,
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input rx1_strobe_in_n,
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input rx1_strobe_in_p,
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input rx2_dclk_in_n,
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input rx2_dclk_in_p,
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output rx2_enable,
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input rx2_idata_in_n,
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input rx2_idata_in_p,
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input rx2_qdata_in_n,
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input rx2_qdata_in_p,
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input rx2_strobe_in_n,
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input rx2_strobe_in_p,
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output tx1_dclk_out_n,
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output tx1_dclk_out_p,
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input tx1_dclk_in_n,
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input tx1_dclk_in_p,
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output tx1_enable,
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output tx1_idata_out_n,
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output tx1_idata_out_p,
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output tx1_qdata_out_n,
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output tx1_qdata_out_p,
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output tx1_strobe_out_n,
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output tx1_strobe_out_p,
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output tx2_dclk_out_n,
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output tx2_dclk_out_p,
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input tx2_dclk_in_n,
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input tx2_dclk_in_p,
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output tx2_enable,
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output tx2_idata_out_n,
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output tx2_idata_out_p,
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output tx2_qdata_out_n,
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output tx2_qdata_out_p,
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output tx2_strobe_out_n,
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output tx2_strobe_out_p,
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input vadj_err,
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output platform_status
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);
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// internal signals
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wire sys_hps_resetn;
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wire sys_resetn_s;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire gpio_rx1_enable_in;
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wire gpio_rx2_enable_in;
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wire gpio_tx1_enable_in;
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wire gpio_tx2_enable_in;
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wire mssi_sync;
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// assignments
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assign platform_status = vadj_err;
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// multi-ssi synchronization
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//
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assign mssi_sync = gpio_o[54];
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assign gpio_i[54:32] = gpio_o[54:32];
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assign gpio_i[55] = vadj_err;
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assign gpio_i[63:56] = gpio_o[63:56];
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// board stuff (max-v-u21)
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assign gpio_i[31:12] = gpio_o[31:12];
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assign gpio_i[11: 4] = gpio_bd_i;
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assign gpio_i[ 3: 0] = gpio_o[ 3: 0];
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assign gpio_bd_o = gpio_o[3:0];
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// peripheral reset
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assign sys_resetn_s = sys_resetn & sys_hps_resetn;
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// instantiations
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
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.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
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.sys_hps_ddr_mem_a (hps_ddr_a),
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.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
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.sys_hps_ddr_mem_ba (hps_ddr_ba),
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.sys_hps_ddr_mem_bg (hps_ddr_bg),
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.sys_hps_ddr_mem_cke (hps_ddr_cke),
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.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
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.sys_hps_ddr_mem_odt (hps_ddr_odt),
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.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
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.sys_hps_ddr_mem_par (hps_ddr_par),
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.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
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.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
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.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
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.sys_hps_ddr_mem_dq (hps_ddr_dq),
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.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
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.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
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.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
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.sys_hps_ddr_rstn_reset_n (sys_resetn),
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.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
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.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
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.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
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.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
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.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
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.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
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.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
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.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
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.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
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.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
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.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
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.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
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.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
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.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
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.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
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.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
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.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
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.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
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.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
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.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
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.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
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.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
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.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
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.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
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.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
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.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
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.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
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.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
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.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
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.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
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.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
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.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
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.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
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.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
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.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
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.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
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.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
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.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
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.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
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.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
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.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
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.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
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.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
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.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
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.sys_hps_out_rstn_reset_n (sys_hps_resetn),
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.sys_hps_rstn_reset_n (sys_resetn),
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.sys_rstn_reset_n (sys_resetn_s),
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.adrv9001_if_rx1_dclk_in_p_dclk_in (rx1_dclk_in_p),
|
||
|
|
.adrv9001_if_rx1_idata_in_n_idata0 (rx1_idata_in_n),
|
||
|
|
.adrv9001_if_rx1_idata_in_p_idata1 (rx1_idata_in_p),
|
||
|
|
.adrv9001_if_rx1_qdata_in_n_qdata2 (rx1_qdata_in_n),
|
||
|
|
.adrv9001_if_rx1_qdata_in_p_qdata3 (rx1_qdata_in_p),
|
||
|
|
.adrv9001_if_rx1_strobe_in_p_strobe_in (rx1_strobe_in_p),
|
||
|
|
.adrv9001_if_rx2_dclk_in_p_dclk_in (rx2_dclk_in_p),
|
||
|
|
.adrv9001_if_rx2_idata_in_n_idata0 (rx2_idata_in_n),
|
||
|
|
.adrv9001_if_rx2_idata_in_p_idata1 (rx2_idata_in_p),
|
||
|
|
.adrv9001_if_rx2_qdata_in_n_qdata2 (rx2_qdata_in_n),
|
||
|
|
.adrv9001_if_rx2_qdata_in_p_qdata3 (rx2_qdata_in_p),
|
||
|
|
.adrv9001_if_rx2_strobe_in_p_strobe_in (rx2_strobe_in_p),
|
||
|
|
.adrv9001_if_tx1_dclk_out_p_dclk_out (tx1_dclk_out_p),
|
||
|
|
.adrv9001_if_tx1_dclk_in_p_dclk_in (tx1_dclk_in_p),
|
||
|
|
.adrv9001_if_tx1_idata_out_n_idata0 (tx1_idata_out_n),
|
||
|
|
.adrv9001_if_tx1_idata_out_p_idata1 (tx1_idata_out_p),
|
||
|
|
.adrv9001_if_tx1_qdata_out_n_qdata2 (tx1_qdata_out_n),
|
||
|
|
.adrv9001_if_tx1_qdata_out_p_qdata3 (tx1_qdata_out_p),
|
||
|
|
.adrv9001_if_tx1_strobe_out_p_strobe_out (tx1_strobe_out_p),
|
||
|
|
.adrv9001_if_tx2_dclk_out_p_dclk_out (tx2_dclk_out_p),
|
||
|
|
.adrv9001_if_tx2_dclk_in_p_dclk_in (tx2_dclk_in_p),
|
||
|
|
.adrv9001_if_tx2_idata_out_n_idata0 (tx2_idata_out_n),
|
||
|
|
.adrv9001_if_tx2_idata_out_p_idata1 (tx2_idata_out_p),
|
||
|
|
.adrv9001_if_tx2_qdata_out_n_qdata2 (tx2_qdata_out_n),
|
||
|
|
.adrv9001_if_tx2_qdata_out_p_qdata3 (tx2_qdata_out_p),
|
||
|
|
.adrv9001_if_tx2_strobe_out_p_strobe_out (tx2_strobe_out_p),
|
||
|
|
|
||
|
|
.adrv9001_if_rx1_enable (rx1_enable),
|
||
|
|
.adrv9001_if_rx2_enable (rx2_enable),
|
||
|
|
.adrv9001_if_tx1_enable (tx1_enable),
|
||
|
|
.adrv9001_if_tx2_enable (tx2_enable),
|
||
|
|
|
||
|
|
.adrv9001_tdd_if_rx1_enable_in (gpio_rx1_enable_in),
|
||
|
|
.adrv9001_tdd_if_rx2_enable_in (gpio_rx2_enable_in),
|
||
|
|
.adrv9001_tdd_if_tx1_enable_in (gpio_tx1_enable_in),
|
||
|
|
.adrv9001_tdd_if_tx2_enable_in (gpio_tx2_enable_in),
|
||
|
|
.adrv9001_tdd_if_tdd_sync_in (1'b0),
|
||
|
|
|
||
|
|
.sys_spi_MISO (spi_do),
|
||
|
|
.sys_spi_MOSI (spi_dio),
|
||
|
|
.sys_spi_SCLK (spi_clk),
|
||
|
|
.sys_spi_SS_n (spi_en),
|
||
|
|
|
||
|
|
.adrv9001_gpio_export({gpio_tx2_enable_in,
|
||
|
|
gpio_tx1_enable_in,
|
||
|
|
gpio_rx2_enable_in,
|
||
|
|
gpio_rx1_enable_in,
|
||
|
|
reset_trx,
|
||
|
|
mode,
|
||
|
|
gp_int,
|
||
|
|
dgpio_11,
|
||
|
|
dgpio_10,
|
||
|
|
dgpio_9,
|
||
|
|
dgpio_8,
|
||
|
|
dgpio_7,
|
||
|
|
dgpio_6,
|
||
|
|
dgpio_5,
|
||
|
|
dgpio_4,
|
||
|
|
dgpio_3,
|
||
|
|
dgpio_2,
|
||
|
|
dgpio_1,
|
||
|
|
dgpio_0})
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
// ***************************************************************************
|
||
|
|
// ***************************************************************************
|