2015-05-11 14:17:07 +00:00
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2015-06-01 14:59:33 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}]
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create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}]
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2015-05-11 14:17:07 +00:00
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derive_pll_clocks
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2015-07-13 14:07:18 +00:00
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derive_clock_uncertainty
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2015-05-11 14:17:07 +00:00
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2015-08-27 17:53:54 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
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