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pluto_hdl_adi/projects/ad9208_dual_ebz/vcu118/Makefile

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ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
makefile: Update dual_ad9208
2019-05-29 06:36:26 +00:00
PROJECT_NAME := ad9208_vcu118
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
M_DEPS += ../common/dual_ad9208_bd.tcl
makefile: Update dual_ad9208
2019-05-29 06:36:26 +00:00
M_DEPS += ../../daq3/common/daq3_spi.v
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
makefile: Update dual_ad9208
2019-05-29 06:36:26 +00:00
LIB_DEPS += jesd204/axi_jesd204_rx
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += util_adcfifo
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
system_id: deployed ip
2019-06-28 08:41:21 +00:00
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
include ../../scripts/project-xilinx.mk