A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

logic-synthesis

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README.md

powerful heightened yielded Logic Synthesis (phyLS)

phyLS is based on the mockturtle and the abc, it can optimize different logics attributes. Currently, it supports mockturtle format(AIG, MIG, XAG, XMG) and abc format(AIG,GIA) based optimization.

Read the documentation here.

Requirements

A modern compiler is required to build the libraries. Compiled successfully with Clang 6.0.1, Clang 12.0.0, GCC 7.3.0, and GCC 8.2.0.

How to Compile

git clone -b aig --recursive https://github.com/panhongyang0/phyLS.git
cd phyLS
mkdir build
cd build
cmake ..
make
./bin/phyLS

baseline scripts

read_aiger ../benchmarks/adder.aig;
ps -a;
resub;
balance;
rewrite;
read_genlib ../src/mcnc.genlib;
techmap;
quit;