From d724f7eea617b55a2d183dca34a8822c995ce731 Mon Sep 17 00:00:00 2001 From: panhongyang Date: Mon, 6 Feb 2023 13:29:42 +0800 Subject: [PATCH] documentation --- docs/Doxyfile | 2 +- docs/balance.rst | 0 docs/cec.rst | 0 docs/changelog.rst | 25 +++++++++++++++++++++++++ docs/create_graph.rst | 0 docs/examples.rst | 4 ++-- docs/exprsim.rst | 0 docs/index.rst | 31 ++++++++++++++++++++++++++++++- docs/load.rst | 0 docs/lut_mapping.rst | 0 docs/lutmap.rst | 0 docs/read.rst | 0 docs/reduction.rst | 0 docs/refactor.rst | 0 docs/requirements.txt | 3 ++- docs/resub.rst | 0 docs/resyn.rst | 0 docs/rewrite.rst | 0 docs/sat.rst | 0 docs/sim.rst | 0 docs/techmap.rst | 0 docs/write.rst | 0 22 files changed, 60 insertions(+), 5 deletions(-) create mode 100644 docs/balance.rst create mode 100644 docs/cec.rst create mode 100644 docs/changelog.rst create mode 100644 docs/create_graph.rst create mode 100644 docs/exprsim.rst create mode 100644 docs/load.rst create mode 100644 docs/lut_mapping.rst create mode 100644 docs/lutmap.rst create mode 100644 docs/read.rst create mode 100644 docs/reduction.rst create mode 100644 docs/refactor.rst create mode 100644 docs/resub.rst create mode 100644 docs/resyn.rst create mode 100644 docs/rewrite.rst create mode 100644 docs/sat.rst create mode 100644 docs/sim.rst create mode 100644 docs/techmap.rst create mode 100644 docs/write.rst diff --git a/docs/Doxyfile b/docs/Doxyfile index aee4d69..11e7211 100644 --- a/docs/Doxyfile +++ b/docs/Doxyfile @@ -58,7 +58,7 @@ PROJECT_LOGO = # entered, it will be relative to the location where doxygen was started. If # left blank the current directory will be used. -OUTPUT_DIRECTORY = +OUTPUT_DIRECTORY = doxyxml # If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- # directories (in 2 levels) under the output directory of each output format and diff --git a/docs/balance.rst b/docs/balance.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/cec.rst b/docs/cec.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/changelog.rst b/docs/changelog.rst new file mode 100644 index 0000000..b5bd1aa --- /dev/null +++ b/docs/changelog.rst @@ -0,0 +1,25 @@ +Change Log +========== + +Next release +------------ + +v1.0 (December 20, 2022) +------------------------ + +* Initial release +* Data structures ``aiger``, ``load``, ``bench``, ``verilog``, ``blif`` +* Logic synthesis commands ``balance`` +* Logic synthesis commands ``resub`` +* Logic resynthesis commands ``resyn`` +* Logic synthesis commands ``rewrite`` +* Logic synthesis commands ``reduction`` +* Logic synthesis commands ``refactor`` + +* Compute truth table for expression ``exprsim`` +* Combinational equivalence checking for AIG network ``cec`` +* SAT solver ``sat`` +* Logic network simulation ``sim`` + +* FPGA technology mapping of the network ``lutmap`` +* Standard cell mapping ``techmap`` diff --git a/docs/create_graph.rst b/docs/create_graph.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/examples.rst b/docs/examples.rst index a5eab28..9a833cc 100644 --- a/docs/examples.rst +++ b/docs/examples.rst @@ -2,7 +2,7 @@ Examples ============ All commands ----------------------------------- +---------------- Input: :: @@ -34,7 +34,7 @@ Output: For more details, simply add '-h' after command to see all options of this command. Synthesis of EPFL benchmarks ----------------------------------- +---------------- In the following example, we show how `phyLS` can be used to synthesize a EPFL benchamrk. diff --git a/docs/exprsim.rst b/docs/exprsim.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/index.rst b/docs/index.rst index 480f086..1090412 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -3,10 +3,39 @@ Welcome to phyLS's documentation! .. toctree:: :maxdepth: 2 - :caption: Contents: + :caption: Contents introduction installation + changelog examples acknowledgments +.. toctree:: + :maxdepth: 2 + :caption: Reference + + load + read + write + balance + create_graph + reduction + refactor + resub + resyn + rewrite + lut_mapping + lutmap + techmap + cec + exprsim + sat + sim + +Indices and tables +================== + +.. * :ref:`genindex` +.. * :ref:`modindex` +.. * :ref:`search` \ No newline at end of file diff --git a/docs/load.rst b/docs/load.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/lut_mapping.rst b/docs/lut_mapping.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/lutmap.rst b/docs/lutmap.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/read.rst b/docs/read.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/reduction.rst b/docs/reduction.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/refactor.rst b/docs/refactor.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/requirements.txt b/docs/requirements.txt index cd6467e..5f067d3 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1 +1,2 @@ -breathe +sphinx==4.0.2 +breathe==4.30.0 diff --git a/docs/resub.rst b/docs/resub.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/resyn.rst b/docs/resyn.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/rewrite.rst b/docs/rewrite.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/sat.rst b/docs/sat.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/sim.rst b/docs/sim.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/techmap.rst b/docs/techmap.rst new file mode 100644 index 0000000..e69de29 diff --git a/docs/write.rst b/docs/write.rst new file mode 100644 index 0000000..e69de29