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@ -4,6 +4,28 @@ Change Log
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Next release
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Next release
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------------
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------------
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v2.0 (August 03, 2023)
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------------------------
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* Semi-tensor product (STP) based k-LUT network simulation ``simulator``, which is faster than ``sim``
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* k-LUT network mapping ``lut_mapping``, default 4-LUT
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* NPN based network Logic synthesis ``rewrite``, faster and more efficient
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* STP-based functional reduction ``stpfr``
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* Logic synthesis commands ``fr``
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* Exact synthesis to find optimal 2-LUTs commands ``exact``
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* 2-LUT rewriting commands ``lutrw``, which enable technology dependent rewriting
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* ABC Logic synthesis commands ``aresub``
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* ABC Logic synthesis commands ``fraig``
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* ABC Logic synthesis commands ``strash``
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* ABC Logic synthesis commands ``comb``
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* ABC Logic synthesis commands ``acec``
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* ABC GIA Logic synthesis commands ``Afraig``
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* ABC GIA Logic synthesis commands ``Aget``
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* convert store element into ABC store ``convert``, which implement conversion between different data structures
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v1.0 (December 20, 2022)
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v1.0 (December 20, 2022)
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------------------------
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------------------------
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@ -11,20 +11,29 @@ Input:
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Output:
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Output:
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::
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::
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ABC commands:
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aresub comb fraig strash
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Verification commands:
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Verification commands:
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cec exprsim sat sim
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acec cec exprsim sat
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sim simulator
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Mapping commands:
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Mapping commands:
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lut_mapping lutmap techmap
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lut_mapping lutmap techmap
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Synthesis commands:
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Synthesis commands:
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balance create_graph reduction refactor
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balance create_graph exact fr
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resub resyn rewrite
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lutrw refactor resub resyn
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rewrite stpfr
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I/O commands:
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I/O commands:
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load read_aiger read_bench read_blif
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load read read_aiger read_bench
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read_genlib read_verilog write_aiger write_bench
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read_blif read_genlib read_gia read_verilog
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write_blif write_dot write_genlib write_verilog
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write write_aiger write_bench write_blif
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write_dot write_genlib write_gia write_verilog
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Gia commands:
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Afraig Aget
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General commands:
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General commands:
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alias convert current help
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alias convert current help
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