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phyLS
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version 3.0

pull/1/head
panhongyang0 2022-12-20 04:36:36 -05:00
parent 60d377336d
commit 67e5c7067b
4 changed files with 275 additions and 0 deletions
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79
src/commands/cec.hpp Normal file
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/* phyLS: powerful heightened yielded Logic Synthesis
* Copyright (C) 2022 */
/**
* @file cec.hpp
*
* @brief performs combinational equivalence checking
*
* @author Homyoung
* @since 2022/12/14
*/
#ifndef CEC_HPP
#define CEC_HPP
#include <mockturtle/algorithms/equivalence_checking.hpp>
#include <mockturtle/algorithms/miter.hpp>
#include <mockturtle/networks/aig.hpp>
#include <mockturtle/networks/xag.hpp>
#include <vector>
using namespace std;
using namespace mockturtle;
namespace alice {
class cec_command : public command {
public:
explicit cec_command(const environment::ptr& env)
: command(env, "combinational equivalence checking for AIG network") {
add_option("file_1, -a", filename_1, "the input file name");
add_option("file_2, -b", filename_2, "the input file name");
add_flag("--verbose, -v", "print the information");
}
protected:
void execute() {
clock_t begin, end;
double totalTime;
begin = clock();
aig_network aig1, aig2;
if ((lorina::read_aiger(filename_1, mockturtle::aiger_reader(aig1)) ==
lorina::return_code::success) &&
(lorina::read_aiger(filename_2, mockturtle::aiger_reader(aig2)) ==
lorina::return_code::success)) {
if (aig1.num_pis() != aig2.num_pis())
std::cerr << "Networks have different number of primary inputs."
<< std::endl
<< "Miter computation has failed." << std::endl;
else {
const auto miter_ntk = *miter<aig_network>(aig1, aig2);
equivalence_checking_stats st;
const auto result = equivalence_checking(miter_ntk, {}, &st);
if (result)
std::cout << "Networks are equivalent." << std::endl;
else
std::cout << "Networks are NOT EQUIVALENT." << std::endl;
}
} else {
std::cerr << "[w] parse error" << std::endl;
}
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
cout.setf(ios::fixed);
cout << "[CPU time] " << setprecision(2) << totalTime << " s" << endl;
}
private:
string filename_1;
string filename_2;
};
ALICE_ADD_COMMAND(cec, "Verification")
} // namespace alice
#endif

104
src/commands/convert_graph.hpp Normal file
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/* phyLS: powerful heightened yielded Logic Synthesis
* Copyright (C) 2022 */
/**
* @file convert_graph.hpp
*
* @brief performs decomposable function for resynthesis graph
*
* @author Homyoung
* @since 2022/12/20
*/
#ifndef CONVERT_GRAPH_HPP
#define CONVERT_GRAPH_HPP
#include <iostream>
#include <mockturtle/algorithms/klut_to_graph.hpp>
using namespace std;
using namespace mockturtle;
namespace alice {
class create_graph_command : public command {
public:
explicit create_graph_command(const environment::ptr& env)
: command(env, "functional reduction : using AIG as default") {
add_option("-e,--expression", expression,
"creates new graph from expression");
add_flag("--mig, -m", "functional reduction for MIG");
add_flag("--xag, -g", "functional reduction for XAG");
add_flag("--xmg, -x", "functional reduction for XMG");
add_flag("--verbose, -v", "print the information");
}
protected:
void execute() {
clock_t begin, end;
double totalTime;
begin = clock();
auto& opt_ntks = store<optimum_network>();
if (opt_ntks.empty()) opt_ntks.extend();
uint32_t num_vars{0u};
for (auto c : expression) {
if (c >= 'a' && c <= 'p')
num_vars = std::max<uint32_t>(num_vars, c - 'a' + 1u);
}
kitty::dynamic_truth_table tt(num_vars);
kitty::create_from_expression(tt, expression);
klut_network kLUT_ntk;
vector<klut_network::signal> children;
for (auto i = 0; i < num_vars; i++) {
const auto x = kLUT_ntk.create_pi();
children.push_back(x);
}
auto fn = [&](kitty::dynamic_truth_table const& remainder,
std::vector<klut_network::signal> const& children) {
return kLUT_ntk.create_node(children, remainder);
};
kLUT_ntk.create_po(dsd_decomposition(kLUT_ntk, tt, children, fn));
if (is_set("mig")) {
auto mig = convert_klut_to_graph<mig_network>(kLUT_ntk);
phyLS::print_stats(mig);
store<mig_network>().extend();
store<mig_network>().current() = mig;
} else if (is_set("xmg")) {
auto xmg = convert_klut_to_graph<xmg_network>(kLUT_ntk);
phyLS::print_stats(xmg);
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
} else if (is_set("xag")) {
auto xag = convert_klut_to_graph<xag_network>(kLUT_ntk);
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = xag;
} else {
auto aig = convert_klut_to_graph<aig_network>(kLUT_ntk);
phyLS::print_stats(aig);
store<aig_network>().extend();
store<aig_network>().current() = aig;
}
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
cout.setf(ios::fixed);
cout << "[CPU time] " << setprecision(2) << totalTime << " s" << endl;
}
private:
string expression = "";
};
ALICE_ADD_COMMAND(create_graph, "Logic synthesis")
} // namespace alice
#endif

89
src/commands/functional_reduction.hpp Normal file
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/* phyLS: powerful heightened yielded Logic Synthesis
* Copyright (C) 2022 */
/**
* @file functional_reduction.hpp
*
* @brief performs functional reduction
*
* @author Homyoung
* @since 2022/12/20
*/
#ifndef FUCNTIONAL_REDUCTION_HPP
#define FUCNTIONAL_REDUCTION_HPP
#include <kitty/static_truth_table.hpp>
#include <mockturtle/algorithms/cleanup.hpp>
#include <mockturtle/algorithms/functional_reduction.hpp>
#include <mockturtle/algorithms/simulation.hpp>
#include <mockturtle/networks/aig.hpp>
#include <mockturtle/networks/mig.hpp>
#include <mockturtle/networks/xag.hpp>
#include <mockturtle/networks/xmg.hpp>
using namespace std;
using namespace mockturtle;
namespace alice {
class reduction_command : public command {
public:
explicit reduction_command(const environment::ptr& env)
: command(env, "functional reduction : using AIG as default") {
add_flag("--mig, -m", "functional reduction for MIG");
add_flag("--xag, -g", "functional reduction for XAG");
add_flag("--xmg, -x", "functional reduction for XMG");
add_flag("--verbose, -v", "print the information");
}
protected:
void execute() {
clock_t begin, end;
double totalTime;
begin = clock();
if (is_set("mig")) {
auto mig = store<mig_network>().current();
functional_reduction(mig);
mig = cleanup_dangling(mig);
phyLS::print_stats(mig);
store<mig_network>().extend();
store<mig_network>().current() = mig;
} else if (is_set("xmg")) {
auto xmg = store<xmg_network>().current();
functional_reduction(xmg);
xmg = cleanup_dangling(xmg);
phyLS::print_stats(xmg);
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
} else if (is_set("xag")) {
auto xag = store<xag_network>().current();
functional_reduction(xag);
xag = cleanup_dangling(xag);
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = xag;
} else {
auto aig = store<aig_network>().current();
functional_reduction(aig);
aig = cleanup_dangling(aig);
phyLS::print_stats(aig);
store<aig_network>().extend();
store<aig_network>().current() = aig;
}
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
cout.setf(ios::fixed);
cout << "[CPU time] " << setprecision(2) << totalTime << " s" << endl;
}
private:
};
ALICE_ADD_COMMAND(reduction, "Logic synthesis")
} // namespace alice
#endif

3
src/phyLS.cpp
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#include "commands/write_dot.hpp" #include "commands/write_dot.hpp"
#include "commands/refactor.hpp" #include "commands/refactor.hpp"
#include "commands/cut_rewriting.hpp" #include "commands/cut_rewriting.hpp"
#include "commands/cec.hpp"
#include "commands/functional_reduction.hpp"
#include "commands/convert_graph.hpp"
ALICE_MAIN(phyLS) ALICE_MAIN(phyLS)