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rewrite

pull/1/head
panhongyang0 2022-12-15 02:27:11 -05:00
parent 78bda87307
commit 60d377336d
4 changed files with 210 additions and 8 deletions
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178
src/commands/cut_rewriting.hpp Normal file
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@ -0,0 +1,178 @@
/* phyLS: powerful heightened yielded Logic Synthesis
* Copyright (C) 2022 */
/**
* @file cut_rewriting.hpp
*
* @brief on-the-fly DAG-aware logic rewriting
*
* @author Homyoung
* @since 2022/12/15
*/
#ifndef CUT_REWRITING_HPP
#define CUT_REWRITING_HPP
#include <time.h>
#include <mockturtle/algorithms/cut_rewriting.hpp>
#include <mockturtle/algorithms/node_resynthesis/akers.hpp>
#include <mockturtle/algorithms/node_resynthesis/exact.hpp>
#include <mockturtle/algorithms/node_resynthesis/mig_npn.hpp>
#include <mockturtle/algorithms/node_resynthesis/xag_minmc2.hpp>
#include <mockturtle/algorithms/node_resynthesis/xag_npn.hpp>
#include <mockturtle/algorithms/node_resynthesis/xmg3_npn.hpp>
#include <mockturtle/networks/aig.hpp>
#include <mockturtle/networks/klut.hpp>
#include <mockturtle/networks/mig.hpp>
#include <mockturtle/networks/xag.hpp>
#include <mockturtle/networks/xmg.hpp>
#include <mockturtle/properties/mccost.hpp>
#include <mockturtle/traits.hpp>
#include <mockturtle/utils/cost_functions.hpp>
#include <mockturtle/views/fanout_view.hpp>
#include "../core/misc.hpp"
using namespace std;
using namespace mockturtle;
namespace alice {
class rewrite_command : public command {
public:
explicit rewrite_command(const environment::ptr& env)
: command(env, "on-the-fly DAG-aware logic rewriting") {
add_flag("--xmg, -x", "rewriting for XMG");
add_flag("--mig, -m", "rewriting for MIG");
add_flag("--xag, -g", "rewriting for XAG");
add_flag("--klut, -l", "rewriting for k-LUT");
add_flag("--akers, -a", "Cut rewriting with Akers synthesis for MIG");
add_flag("--compatibility_graph, -c", "In-place cut rewriting");
add_flag("--verbose, -v", "print the information");
}
protected:
void execute() {
clock_t begin, end;
double totalTime;
if (is_set("xmg")) {
if (store<xmg_network>().size() == 0u)
std::cerr << "Error: Empty XMG network\n";
else {
auto xmg = store<xmg_network>().current();
begin = clock();
xmg_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
if (is_set("compatibility_graph"))
cut_rewriting_with_compatibility_graph(xmg, resyn, ps);
else
xmg = cut_rewriting(xmg, resyn, ps);
xmg = cleanup_dangling(xmg);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(xmg);
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
}
} else if (is_set("mig")) {
if (store<mig_network>().size() == 0u)
std::cerr << "Error: Empty MIG network\n";
else {
auto mig = store<mig_network>().current();
begin = clock();
if (is_set("akers")) {
akers_resynthesis<mig_network> resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
if (is_set("compatibility_graph"))
cut_rewriting_with_compatibility_graph(mig, resyn, ps);
else
mig = cut_rewriting(mig, resyn, ps);
} else {
mig_npn_resynthesis resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
if (is_set("compatibility_graph"))
cut_rewriting_with_compatibility_graph(mig, resyn, ps);
else
mig = cut_rewriting(mig, resyn, ps);
}
mig = cleanup_dangling(mig);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(mig);
store<mig_network>().extend();
store<mig_network>().current() = mig;
}
} else if (is_set("xag")) {
if (store<xag_network>().size() == 0u)
std::cerr << "Error: Empty XAG network\n";
else {
auto xag = store<xag_network>().current();
begin = clock();
xag_npn_resynthesis<xag_network> resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4u;
ps.min_cand_cut_size = 2;
ps.min_cand_cut_size_override = 3;
if (is_set("compatibility_graph")) {
cut_rewriting_with_compatibility_graph(xag, resyn, ps, nullptr,
mc_cost<xag_network>());
} else {
xag = cut_rewriting(xag, resyn, ps);
}
xag = cleanup_dangling(xag);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = xag;
}
} else if (is_set("klut")) {
if (store<klut_network>().size() == 0u)
std::cerr << "Error: Empty k-LUT network\n";
else {
auto klut = store<klut_network>().current();
begin = clock();
exact_resynthesis resyn(3u);
if (is_set("compatibility_graph"))
cut_rewriting_with_compatibility_graph(klut, resyn);
else
klut = cut_rewriting(klut, resyn);
klut = cleanup_dangling(klut);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(klut);
store<klut_network>().extend();
store<klut_network>().current() = klut;
}
} else {
if (store<aig_network>().size() == 0u)
std::cerr << "Error: Empty AIG network\n";
else {
auto aig = store<aig_network>().current();
begin = clock();
xag_npn_resynthesis<aig_network> resyn;
cut_rewriting_params ps;
ps.cut_enumeration_ps.cut_size = 4;
aig = cut_rewriting(aig, resyn, ps);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(aig);
store<aig_network>().extend();
store<aig_network>().current() = aig;
}
}
cout.setf(ios::fixed);
cout << "[CPU time] " << setprecision(2) << totalTime << " s" << endl;
}
};
ALICE_ADD_COMMAND(rewrite, "Logic synthesis")
} // namespace alice
#endif

7
src/commands/node_resynthesis.hpp
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@ -40,7 +40,8 @@ class resyn_command : public command {
public:
explicit resyn_command(const environment::ptr& env)
: command(env,
"performs technology-independent restructuring : using MIG as default") {
"performs technology-independent restructuring : using MIG as "
"default") {
add_flag("--xmg, -x", "Resubstitution for XMG");
add_flag("--xag, -g", "Resubstitution for XAG");
add_flag("--direct, -d", "Node resynthesis with direct synthesis");
@ -74,8 +75,8 @@ class resyn_command : public command {
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
} else if (is_set("xag")) {
begin = clock();
direct_resynthesis<xag_network> xag_resyn;
const auto xag = node_resynthesis<xag_network>(klut, xag_resyn);
xag_npn_resynthesis<xag_network> resyn;
const auto xag = node_resynthesis<xag_network>(klut, resyn);
store<xag_network>().extend();
store<xag_network>().current() = cleanup_dangling(xag);
phyLS::print_stats(xag);

32
src/commands/refactor.hpp
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@ -49,14 +49,21 @@ class refactor_command : public command {
std::cerr << "Error: Empty MIG network\n";
else {
auto mig = store<mig_network>().current();
begin = clock();
if (is_set("akers")) {
akers_resynthesis<mig_network> resyn;
refactoring(mig, resyn);
refactoring_params ps;
ps.max_pis = 4u;
refactoring(mig, resyn, ps);
} else {
mig_npn_resynthesis resyn;
refactoring(mig, resyn);
refactoring_params ps;
ps.max_pis = 4u;
refactoring(mig, resyn, ps);
}
mig = cleanup_dangling(mig);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(mig);
store<mig_network>().extend();
store<mig_network>().current() = mig;
@ -66,9 +73,14 @@ class refactor_command : public command {
std::cerr << "Error: Empty XAG network\n";
else {
auto xag = store<xag_network>().current();
begin = clock();
bidecomposition_resynthesis<xag_network> resyn;
refactoring(xag, resyn);
refactoring_params ps;
ps.max_pis = 4u;
refactoring(xag, resyn, ps);
xag = cleanup_dangling(xag);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(xag);
store<xag_network>().extend();
store<xag_network>().current() = xag;
@ -78,9 +90,14 @@ class refactor_command : public command {
std::cerr << "Error: Empty XMG network\n";
else {
auto xmg = store<xmg_network>().current();
begin = clock();
xmg_npn_resynthesis resyn;
refactoring(xmg, resyn);
refactoring_params ps;
ps.max_pis = 4u;
refactoring(xmg, resyn, ps);
xmg = cleanup_dangling(xmg);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(xmg);
store<xmg_network>().extend();
store<xmg_network>().current() = xmg;
@ -90,9 +107,14 @@ class refactor_command : public command {
std::cerr << "Error: Empty AIG network\n";
else {
auto aig = store<aig_network>().current();
begin = clock();
direct_resynthesis<aig_network> aig_resyn;
refactoring(aig, aig_resyn);
refactoring_params ps;
ps.max_pis = 4u;
refactoring(aig, aig_resyn, ps);
aig = cleanup_dangling(aig);
end = clock();
totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
phyLS::print_stats(aig);
store<aig_network>().extend();
store<aig_network>().current() = aig;

1
src/phyLS.cpp
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@ -35,5 +35,6 @@
#include "commands/techmap.hpp"
#include "commands/write_dot.hpp"
#include "commands/refactor.hpp"
#include "commands/cut_rewriting.hpp"
ALICE_MAIN(phyLS)