update xag optimziation
parent
33e191e2d5
commit
52d20f4c9f
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@ -34,6 +34,7 @@ class balance_command : public command {
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: command(env,
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"transforms the current network into a well-balanced AIG") {
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add_flag("--xmg, -x", "Balance for XMG");
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add_flag("--xag, -g", "ESOP balance for XAG");
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add_flag("--strash, -s", "Balance AND finding structural hashing");
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add_flag("--verbose, -v", "print the information");
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}
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@ -42,6 +43,8 @@ class balance_command : public command {
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void execute() {
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clock_t begin, end;
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double totalTime = 0.0;
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begin = clock();
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if (is_set("xmg")) {
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xmg_network xmg = store<xmg_network>().current();
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xmg = balancing(
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@ -53,31 +56,33 @@ class balance_command : public command {
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store<xmg_network>().extend();
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store<xmg_network>().current() = xmg_copy;
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} else if (is_set("xag")) {
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xag_network xag = store<xag_network>().current();
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xag_network res = esop_balancing(xag);
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phyLS::print_stats(res);
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store<xag_network>().extend();
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store<xag_network>().current() = res;
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} else {
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if (store<aig_network>().size() == 0u)
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std::cerr << "Error: Empty AIG network\n";
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else {
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auto aig = store<aig_network>().current();
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if (is_set("strash")) {
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begin = clock();
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aig_balancing_params ps;
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ps.minimize_levels = false;
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aig_balance(aig, ps);
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end = clock();
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totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
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} else {
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begin = clock();
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aig_balance(aig);
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end = clock();
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totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
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}
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phyLS::print_stats(aig);
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store<aig_network>().extend();
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store<aig_network>().current() = aig;
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}
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}
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end = clock();
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totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
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cout.setf(ios::fixed);
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cout << "[CPU time] " << setprecision(2) << totalTime << " s" << endl;
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}
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@ -47,9 +47,7 @@ class lut_mapping_command : public command {
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clock_t begin, end;
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double totalTime;
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lut_mapping_params ps;
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if (is_set("area")){
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ps.rounds_ela = 4u;
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}
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if (is_set("area")) ps.rounds = 0u;
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if (is_set("mig")) {
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/* derive some MIG */
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@ -32,8 +32,9 @@ class lutmap_command : public command {
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add_flag("--mig, -m", "FPGA technology mapping for MIG");
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add_flag("--xag, -g", "FPGA technology mapping for XAG");
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add_flag("--xmg, -x", "FPGA technology mapping for XMG");
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add_flag("--klut, -k", "FPGA technology mapping for k-LUT");
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add_option("--cut_size, -s", cut_size,
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"Maximum number of leaves for a cut [default = 4]");
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"Maximum number of leaves for a cut [default = 6]");
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add_option(
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"--cut_limit, -l", cut_limit,
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"the input Maximum number of cuts for a node name [default = 25]");
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@ -47,6 +48,7 @@ class lutmap_command : public command {
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"LUT map with cost function [default = false]");
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add_flag("--dominated_cuts, -d",
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"Remove the cuts that are contained in others [default = true]");
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add_option("--output, -o", filename, "the bench filename");
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add_flag("--verbose, -v", "print the information");
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}
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@ -119,6 +121,24 @@ class lutmap_command : public command {
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phyLS::lut_map(mapped_xmg, ps);
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mapped_xmg.clear_mapping();
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}
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} else if (is_set("klut")) {
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if (store<klut_network>().size() == 0u)
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std::cerr << "Error: Empty k-LUT network\n";
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else {
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auto klut = store<klut_network>().current();
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mapping_view mapped_klut{klut};
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phyLS::lut_map_params ps;
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if (is_set("area")) ps.area_oriented_mapping = true;
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if (is_set("relax_required")) ps.relax_required = relax_required;
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if (is_set("cut_size")) ps.cut_enumeration_ps.cut_size = cut_size;
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if (is_set("cut_limit")) ps.cut_enumeration_ps.cut_limit = cut_limit;
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if (is_set("recompute_cuts")) ps.recompute_cuts = false;
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if (is_set("edge")) ps.edge_optimization = false;
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if (is_set("dominated_cuts")) ps.remove_dominated_cuts = false;
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cout << "Mapped kLUT into " << cut_size << "-LUT : ";
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phyLS::lut_map(mapped_klut, ps);
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mapped_klut.clear_mapping();
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}
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} else {
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if (store<aig_network>().size() == 0u)
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std::cerr << "Error: Empty AIG network\n";
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@ -139,7 +159,11 @@ class lutmap_command : public command {
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mapped_aig, ps);
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else
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phyLS::lut_map(mapped_aig, ps);
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mapped_aig.clear_mapping();
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if (is_set("output")) {
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write_bench(mapped_aig, filename);
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} else {
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mapped_aig.clear_mapping();
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}
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}
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}
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}
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@ -148,6 +172,7 @@ class lutmap_command : public command {
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uint32_t cut_size{6u};
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uint32_t cut_limit{8u};
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uint32_t relax_required{0u};
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std::string filename = "lut.bench";
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};
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ALICE_ADD_COMMAND(lutmap, "Mapping")
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@ -31,6 +31,7 @@
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#include <mockturtle/networks/xmg.hpp>
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#include "../core/misc.hpp"
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#include "../networks/aoig/xag_lut_npn.hpp"
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using namespace std;
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using namespace mockturtle;
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@ -75,7 +76,7 @@ class resyn_command : public command {
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totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
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} else if (is_set("xag")) {
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begin = clock();
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xag_npn_resynthesis<xag_network> resyn;
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xag_npn_lut_resynthesis resyn;
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const auto xag = node_resynthesis<xag_network>(klut, resyn);
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store<xag_network>().extend();
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store<xag_network>().current() = cleanup_dangling(xag);
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@ -33,10 +33,13 @@ class refactor_command : public command {
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explicit refactor_command(const environment::ptr& env)
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: command(env,
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"performs technology-independent refactoring [default = AIG]") {
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add_option("--cut_size, -k", cut_size,
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"Maximum number of PIs of the MFFC or window");
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add_flag("--mig, -m", "refactoring for MIG");
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add_flag("--xag, -g", "refactoring for XAG");
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add_flag("--xmg, -x", "refactoring for XMG");
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add_flag("--akers, -a", "Refactoring with Akers synthesis for MIG");
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add_flag("--gain, -n", "optimize until there is no gain");
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add_flag("--verbose, -v", "print the information");
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}
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@ -54,12 +57,12 @@ class refactor_command : public command {
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if (is_set("akers")) {
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akers_resynthesis<mig_network> resyn;
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refactoring_params ps;
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ps.max_pis = 4u;
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ps.max_pis = cut_size;
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refactoring(mig, resyn, ps);
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} else {
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mig_npn_resynthesis resyn;
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refactoring_params ps;
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ps.max_pis = 4u;
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ps.max_pis = cut_size;
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refactoring(mig, resyn, ps);
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}
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mig = cleanup_dangling(mig);
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@ -77,7 +80,7 @@ class refactor_command : public command {
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begin = clock();
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bidecomposition_resynthesis<xag_network> resyn;
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refactoring_params ps;
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ps.max_pis = 4u;
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ps.max_pis = cut_size;
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refactoring(xag, resyn, ps);
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xag = cleanup_dangling(xag);
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end = clock();
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@ -92,11 +95,23 @@ class refactor_command : public command {
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else {
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auto xmg = store<xmg_network>().current();
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begin = clock();
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xmg_npn_resynthesis resyn;
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refactoring_params ps;
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ps.max_pis = 4u;
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refactoring(xmg, resyn, ps);
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xmg = cleanup_dangling(xmg);
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if (is_set("gain")) {
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uint64_t size_current{};
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do {
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size_current = xmg.num_gates();
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xmg_npn_resynthesis resyn;
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refactoring_params ps;
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ps.max_pis = cut_size;
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refactoring(xmg, resyn, ps);
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xmg = cleanup_dangling(xmg);
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} while (xmg.num_gates() < size_current);
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} else {
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xmg_npn_resynthesis resyn;
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refactoring_params ps;
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ps.max_pis = cut_size;
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refactoring(xmg, resyn, ps);
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xmg = cleanup_dangling(xmg);
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}
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end = clock();
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totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
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phyLS::print_stats(xmg);
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@ -111,7 +126,7 @@ class refactor_command : public command {
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begin = clock();
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direct_resynthesis<aig_network> aig_resyn;
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refactoring_params ps;
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ps.max_pis = 4u;
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ps.max_pis = cut_size;
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refactoring(aig, aig_resyn, ps);
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aig = cleanup_dangling(aig);
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end = clock();
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@ -127,6 +142,7 @@ class refactor_command : public command {
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}
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private:
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uint32_t cut_size = 4u;
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};
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ALICE_ADD_COMMAND(refactor, "Synthesis")
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@ -34,8 +34,9 @@ class write_npz_command : public command {
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add_option("--csv, -c", filename_csv,
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"The path to store csv file, default: ./placement/test.csv");
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add_option("--def, -d", filename_def,
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"The path to store def file, default: "
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"./placement/mfloorplan.def & ./placement/floorplan.def");
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"The path to store def file, default: ./placement/floorplan.def");
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add_option("--mdef, -f", filename_mdef,
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"The path to store def file, default: ./placement/mfloorplan.def");
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}
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protected:
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@ -50,10 +51,9 @@ class write_npz_command : public command {
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aig_network aig = store<aig_network>().current();
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if (is_set("csv")) {
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phyLS::write_npz(aig, filename_csv);
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} else if (is_set("def")) {
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}
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if (is_set("def")) {
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phyLS::write_def(aig, filename_def, filename_mdef);
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} else {
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assert(false && "At least one filename should be specified. ");
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}
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}
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}
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@ -39,6 +39,7 @@ class wr_command : public command {
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"set the cut size from 2 to 6, default = 4");
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add_option("num_levels, -l", num_levels,
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"set the window level, default = 5");
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add_flag("--xag, -a", "indow rewriting for XAG");
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add_flag("--gain, -g", "optimize until there is no gain");
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add_flag("--resub, -r", "window resub");
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add_flag("--verbose, -v", "print the information");
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@ -48,44 +49,69 @@ class wr_command : public command {
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void execute() {
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clock_t begin, end;
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double totalTime;
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begin = clock();
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auto aig = store<aig_network>().current();
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window_rewriting_params ps;
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ps.cut_size = cut_size;
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ps.num_levels = num_levels;
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if (is_set("resub")) {
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window_resub_params ps_r;
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if (is_set("xag")) {
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xag_network xag = store<xag_network>().current();
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window_rewriting_params ps;
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ps.cut_size = cut_size;
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ps.num_levels = num_levels;
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if (is_set("gain")) {
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window_aig_enumerative_resub(aig, ps_r);
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} else {
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window_aig_heuristic_resub(aig, ps_r);
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}
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aig = cleanup_dangling(aig);
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} else {
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if (is_set("gain")) {
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uint64_t const size_before{aig.num_gates()};
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uint64_t size_current{};
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do {
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size_current = aig.num_gates();
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size_current = xag.num_gates();
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window_rewriting_stats win_st;
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window_rewriting(aig, ps, &win_st);
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window_rewriting(xag, ps, &win_st);
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if (is_set("verbose")) win_st.report();
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aig = cleanup_dangling(aig);
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} while (aig.num_gates() < size_current);
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xag = cleanup_dangling(xag);
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} while (xag.num_gates() < size_current);
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} else {
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window_rewriting_stats win_st;
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window_rewriting(aig, ps, &win_st);
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aig = cleanup_dangling(aig);
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window_rewriting(xag, ps, &win_st);
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xag = cleanup_dangling(xag);
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}
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phyLS::print_stats(xag);
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store<xag_network>().extend();
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store<xag_network>().current() = xag;
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} else {
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if (store<aig_network>().size() == 0u)
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std::cerr << "Error: Empty AIG network\n";
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else {
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auto aig = store<aig_network>().current();
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window_rewriting_params ps;
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ps.cut_size = cut_size;
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ps.num_levels = num_levels;
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if (is_set("resub")) {
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window_resub_params ps_r;
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if (is_set("gain")) {
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window_aig_enumerative_resub(aig, ps_r);
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} else {
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window_aig_heuristic_resub(aig, ps_r);
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}
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aig = cleanup_dangling(aig);
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} else {
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if (is_set("gain")) {
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uint64_t size_current{};
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do {
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size_current = aig.num_gates();
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window_rewriting_stats win_st;
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window_rewriting(aig, ps, &win_st);
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if (is_set("verbose")) win_st.report();
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aig = cleanup_dangling(aig);
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} while (aig.num_gates() < size_current);
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} else {
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window_rewriting_stats win_st;
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window_rewriting(aig, ps, &win_st);
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aig = cleanup_dangling(aig);
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}
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}
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phyLS::print_stats(aig);
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store<aig_network>().extend();
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store<aig_network>().current() = aig;
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}
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}
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phyLS::print_stats(aig);
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store<aig_network>().extend();
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store<aig_network>().current() = aig;
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end = clock();
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totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
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@ -31,28 +31,38 @@ namespace phyLS {
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template <class Ntk>
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void write_npz(Ntk const& ntk, std::ostream& os) {
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std::stringstream connect;
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cout << "num_pis: " << ntk.num_pis() << endl;
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cout << "num_pos: " << ntk.num_pos() << endl;
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cout << "num_gates: " << ntk.num_gates() << endl;
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// cout << "num_pis: " << ntk.num_pis() << endl;
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// cout << "num_pos: " << ntk.num_pos() << endl;
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// cout << "num_gates: " << ntk.num_gates() << endl;
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int num_pis = ntk.num_pis(), num_pos = ntk.num_pos(),
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num_gates = ntk.num_gates();
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int size = num_pis + num_pos + num_gates;
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vector<vector<double>> adj(size, vector<double>(size, 0));
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cout << "size: " << size << endl;
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vector<double> value;
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vector<vector<int>> coordinate(2);
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ntk.foreach_node([&](auto const& n) {
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if (ntk.is_constant(n) || ntk.is_ci(n)) return true;
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ntk.foreach_fanin(n, [&](auto const& f) {
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if (ntk.node_to_index(ntk.get_node(f)) <= num_pis) {
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adj[ntk.node_to_index(n) - num_pis - 1]
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[ntk.node_to_index(ntk.get_node(f)) + num_gates - 1] = 1;
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adj[ntk.node_to_index(ntk.get_node(f)) + num_gates - 1]
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[ntk.node_to_index(n) - num_pis - 1] = 1;
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value.push_back(0.6);
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coordinate[0].push_back(ntk.node_to_index(n) - num_pis - 1);
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coordinate[1].push_back(ntk.node_to_index(ntk.get_node(f)) + num_gates -
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1);
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value.push_back(0.6);
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coordinate[0].push_back(ntk.node_to_index(ntk.get_node(f)) + num_gates -
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1);
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coordinate[1].push_back(ntk.node_to_index(n) - num_pis - 1);
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} else {
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adj[ntk.node_to_index(n) - num_pis - 1]
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[ntk.node_to_index(ntk.get_node(f)) - num_pis - 1] = 0.5;
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adj[ntk.node_to_index(ntk.get_node(f)) - num_pis - 1]
|
||||
[ntk.node_to_index(n) - num_pis - 1] = 0.5;
|
||||
value.push_back(1);
|
||||
coordinate[0].push_back(ntk.node_to_index(n) - num_pis - 1);
|
||||
coordinate[1].push_back(ntk.node_to_index(ntk.get_node(f)) - num_pis -
|
||||
1);
|
||||
value.push_back(1);
|
||||
coordinate[0].push_back(ntk.node_to_index(ntk.get_node(f)) - num_pis -
|
||||
1);
|
||||
coordinate[1].push_back(ntk.node_to_index(n) - num_pis - 1);
|
||||
}
|
||||
return true;
|
||||
});
|
||||
|
@ -61,19 +71,33 @@ void write_npz(Ntk const& ntk, std::ostream& os) {
|
|||
|
||||
ntk.foreach_po([&](auto const& f, auto i) {
|
||||
if (ntk.node_to_index(ntk.get_node(f)) <= num_pis) {
|
||||
adj[i + num_pis + num_gates]
|
||||
[ntk.node_to_index(ntk.get_node(f)) + num_gates - 1] = 1;
|
||||
adj[ntk.node_to_index(ntk.get_node(f)) + num_gates - 1]
|
||||
[i + num_pis + num_gates] = 1;
|
||||
value.push_back(0.1);
|
||||
coordinate[0].push_back(i + num_pis + num_gates);
|
||||
coordinate[1].push_back(ntk.node_to_index(ntk.get_node(f)) + num_gates -
|
||||
1);
|
||||
value.push_back(0.1);
|
||||
coordinate[0].push_back(ntk.node_to_index(ntk.get_node(f)) + num_gates -
|
||||
1);
|
||||
coordinate[1].push_back(i + num_pis + num_gates);
|
||||
} else {
|
||||
adj[i + num_pis + num_gates]
|
||||
[ntk.node_to_index(ntk.get_node(f)) - num_pis - 1] = 0.5;
|
||||
adj[ntk.node_to_index(ntk.get_node(f)) - num_pis - 1]
|
||||
[i + num_pis + num_gates] = 0.5;
|
||||
value.push_back(0.6);
|
||||
coordinate[0].push_back(i + num_pis + num_gates);
|
||||
coordinate[1].push_back(ntk.node_to_index(ntk.get_node(f)) - num_pis - 1);
|
||||
value.push_back(0.6);
|
||||
coordinate[0].push_back(ntk.node_to_index(ntk.get_node(f)) - num_pis - 1);
|
||||
coordinate[1].push_back(i + num_pis + num_gates);
|
||||
}
|
||||
});
|
||||
|
||||
for (auto x : adj) {
|
||||
for (int i = 0; i < value.size(); i++) {
|
||||
if (i == value.size() - 1) {
|
||||
connect << fmt::format("{}", value[i]);
|
||||
} else {
|
||||
connect << fmt::format("{}", value[i]) << ",";
|
||||
}
|
||||
}
|
||||
connect << "\n";
|
||||
for (auto x : coordinate) {
|
||||
for (int i = 0; i < x.size(); i++) {
|
||||
if (i == x.size() - 1) {
|
||||
connect << fmt::format("{}", x[i]);
|
||||
|
@ -89,9 +113,9 @@ void write_npz(Ntk const& ntk, std::ostream& os) {
|
|||
template <class Ntk>
|
||||
void write_def(Ntk const& ntk, std::ostream& os_def, std::ostream& os_mdef) {
|
||||
std::stringstream components, pins, pins_def;
|
||||
cout << "num_pis: " << ntk.num_pis() << endl;
|
||||
cout << "num_pos: " << ntk.num_pos() << endl;
|
||||
cout << "num_gates: " << ntk.num_gates() << endl;
|
||||
// cout << "num_pis: " << ntk.num_pis() << endl;
|
||||
// cout << "num_pos: " << ntk.num_pos() << endl;
|
||||
// cout << "num_gates: " << ntk.num_gates() << endl;
|
||||
int num_pis = ntk.num_pis(), num_pos = ntk.num_pos(),
|
||||
num_gates = ntk.num_gates();
|
||||
int size = num_pis + num_pos + num_gates;
|
||||
|
|
|
@ -73,7 +73,7 @@ class stp_npn_resynthesis {
|
|||
std::unordered_map<std::string, std::vector<std::string>> opt_klut;
|
||||
|
||||
void load_optimal_klut() {
|
||||
std::ifstream infile("../src/networks/stp/opt_map.txt");
|
||||
std::ifstream infile("../src/networks/stp/opt_stp.txt");
|
||||
if (!infile) {
|
||||
std::cout << " Cannot open file " << std::endl;
|
||||
assert(false);
|
||||
|
|
|
@ -77,7 +77,7 @@
|
|||
#include "commands/xmg/xmgrs.hpp"
|
||||
#include "commands/xmg/xmgrw.hpp"
|
||||
#include "commands/exact/exact_multi.hpp"
|
||||
#include "commands/to_npz.hpp"
|
||||
// #include "commands/exact/exact_klut.hpp"
|
||||
// #include "commands/exact/exactlut.hpp"
|
||||
// #include "commands/to_npz.hpp"
|
||||
ALICE_MAIN(phyLS)
|
Loading…
Reference in New Issue