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-Subproject commit 581c58b9c48772b549dc921fd7c854484470ed8c

docs/balance.rst

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+Balance
+=============
+
+**Header:** ``mockturtle/algorithms/balancing.hpp``
+
+Balancing of a logic network
+
+This function implements a dynamic-programming and cut-enumeration based balancing algorithm. 
+It returns a new network of the same type and performs generic balancing by providing a rebalancing function.

docs/cec.rst

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+Cec
+=============
+
+**Header:** ``mockturtle/algorithms/equivalence_checking.hpp``
+
+Combinational equivalence checking.
+
+This function expects as input a miter circuit that can be generated, e.g., with the function miter. 
+It returns an optional which is nullopt, if no solution can be found, this happens when a resource limit is set using the function parameters. 
+Otherwise it returns true, if the miter is equivalent or false, if the miter is not equivalent. 
+In the latter case the counter example is written to the statistics pointer as a std::vector<bool> following the same order as the primary inputs.

docs/create_graph.rst

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+Create_graph
+=============
+
+**Header:** ``mockturtle/algorithms/klut_to_graph.hpp``
+
+This header file implements utility functions to convert a :math:`k`-LUT network into a
+homogeneous graph network, such as AIG, XAG, MIG or XMG. It wraps around three node resynthesis strategies for the user.
+
+First the function attempts a Disjoint Support Decomposition (DSD), branching the network into subnetworks. 
+As soon as DSD can no longer be done, there are two possibilities depending on the dimensionality of the subnetwork to be resynthesized.
+On the one hand, if the size of the associated support is lower or equal than 4, the solution can be recovered by exploiting the mapping of the subnetwork to its NPN-class. 
+On the other hand, if the support size is higher than 4, A Shannon decomposition is performed, branching the network in further subnetworks with reduced support.
+Finally, once the threshold value of 4 is reached, the NPN mapping completes the graph definition.
+
+There is an out-of-place version, and an in-place version of the function.
+
+The following example shows how to convert a :math:`k`-LUT network into an AIG, a XAG, a MIG and a XMG.
+
+.. code-block:: c++
+
+   /* derive some k-LUT */
+   const klut_network klut = ...;
+
+   /* out-of-place version */
+   aig_network aig = convert_klut_to_graph<aig_network>( klut );
+   xag_network xag = convert_klut_to_graph<xag_network>( klut );
+
+   /* in-place version */
+   mig_network mig;
+   xmg_network xmg;
+   convert_klut_to_graph<mig_network>( mig, klut );
+   convert_klut_to_graph<xmg_network>( xmg, klut );

docs/load.rst

@@ -3,3 +3,6 @@ Load
 
 The header ``<src/commands/load.hpp>`` implements methods to load 
 a hexdecimal string represented truth table.
+
+It implements a dynamic truth table by the header ``<kitty/dynamic_truth_table.hpp>``. 
+A dynamic truth table can be initialized with a number of variables that is computed at runtime.

docs/lut_mapping.rst

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+Lut_mapping
+=============
+
+**Header:** ``mockturtle/algorithms/collapse_mapped.hpp``
+
+Collapse mapped network into k-LUT network.
+
+Collapses a mapped network into a k-LUT network. In the mapped network each cell is represented in terms of a collection of nodes from the subject graph. This method creates a new network in which each cell is represented by a single node.
+
+This function performs some optimizations with respect to possible output complementations in the subject graph:
+
+If an output driver is only used in positive form, nothing changes
+
+If an output driver is only used in complemented form, the cell function of the node is negated.
+
+If an output driver is used in both forms, two nodes will be created for the mapped node.

docs/lutmap.rst

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+Lutmap
+=============
+
+**Header:** ``mockturtle/algorithms/lut_mapper.hpp``
+
+LUT mapping with cut size :math:`k` partitions a logic network into mapped
+nodes and unmapped nodes, where a mapped node :math:`n` is assigned some cut
+:math:`(n, L)` such that the following conditions hold: i) each node that
+drives a primary output is mapped, and ii) each leaf in the cut of a mapped
+node is either a primary input or also mapped.  This ensures that the mapping
+covers the whole logic network.  LUT mapping aims to find a good mapping with
+respect to a cost function, e.g., a short critical path in the mapping or a
+small number of mapped nodes.  The LUT mapping algorithm can assign a weight
+to a cut for alternative cost functions.
+
+This implementation offers delay- or area-oriented mapping. The mapper can be
+configured using many options.

docs/read.rst

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+Read
+=============
+
+The phyLS implements several reader callbacks that can be used with the lorina_ library.
+The header ``mockturtle/io/<format>_reader.hpp`` implements the reader callback ``<format>_reader``.
+
+Example:
+::
+    read_aiger xxx.aig; // read an aiger as input
+
+.. _lorina: https://github.com/hriener/lorina

docs/reduction.rst

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+Reduction
+=============
+
+**Header:** ``mockturtle/algorithms/functional_reduction.hpp``
+
+The following example shows how to perform functional reduction
+to remove constant nodes and functionally equivalent nodes in
+the network.
+
+.. code-block:: c++
+
+   /* derive some AIG */
+   aig_network aig = ...;
+
+   functional_reduction( aig );

docs/refactor.rst

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+Refactor
+=============
+
+**Header:** ``mockturtle/algorithms/refactoring.hpp``
+
+It is possible to change the cost function of nodes in refactoring.  Here is
+an example, in which the cost function does not account for XOR gates in a network. 
+This may be helpful in logic synthesis addressing cryptography applications where
+XOR gates are considered "for free". 

docs/resub.rst

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+Resub
+=============
+
+**Header:** ``mockturtle/algorithms/resubstitution.hpp``
+
+Several resubstitution algorithms are implemented and can be called directly, including:
+
+- ``default_resubstitution`` does functional reduction within a window.
+
+- ``aig_resubstitution``, ``mig_resubstitution`` and ``xmg_resubstitution`` do window-based resubstitution in the corresponding network types.
+
+- ``resubstitution_minmc_withDC`` minimizes multiplicative complexity in XAGs with window-based resubstitution.
+
+- ``sim_resubstitution`` does simulation-guided resubstitution in AIGs or XAGs.

docs/resyn.rst

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+Resyn
+=============
+
+**Headers:** ``mockturtle/algorithms/resyn_engines/mig_resyn.hpp``, ``mockturtle/algorithms/resyn_engines/xag_resyn.hpp``
+
+The problem of *logic resynthesis* is defined as follows:
+
+Given a *target* function :math:`f` and a set of *divisor* functions :math:`g_1, ..., g_n`, find a *dependency function* :math:`h` such that :math:`f=h(g_1, ..., g_n)`.
+
+Specifically, the dependency function is represented by a *dependency circuit* of a certain network type and we aim at finding a small dependency circuit.
+The logic resynthesis engines can be used in resubstitution to find the replacement for the root node. 
+Interfacing resubstitution functors (see :ref:`resubstitution_structure` of the resubstitution framework) are provided in ``mockturtle/algorithms/mig_resub.hpp`` and ``mockturtle/algorithms/sim_resub.hpp``.

docs/rewrite.rst

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+Rewrite
+=============
+
+**Header:** ``mockturtle/algorithms/mig_algebraic_rewriting.hpp``
+
+**Header:** ``mockturtle/algorithms/xag_algebraic_rewriting.hpp``
+
+
+Majority algebraic depth rewriting.
+
+This algorithm tries to rewrite a network with majority gates for depth optimization using the associativity and distributivity rule in majority-of-3 logic. 
+It can be applied to networks other than MIGs, but only considers pairs of nodes which both implement the majority-of-3 function.

docs/sim.rst

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+Sim
+=============
+
+**Header:** ``mockturtle/algorithms/simulation.hpp``
+
+Simulates a network with a generic simulator.
+This is a generic simulation algorithm that can simulate arbitrary values. 
+
+The following simulators are implemented:
+
+* ``mockturtle::default_simulator<bool>``: This simulator simulates Boolean
+  values.  A vector with assignments for each primary input must be passed to
+  the constructor.
+* ``mockturtle::default_simulator<kitty::static_truth_table<NumVars>>``: This
+  simulator simulates truth tables.  Each primary input is assigned the
+  projection function according to the index.  The number of variables must be
+  known at compile time.
+* ``mockturtle::default_simulator<kitty::dynamic_truth_table>``: This simulator
+  simulates truth tables.  Each primary input is assigned the projection
+  function according to the index.  The number of variables be passed to the
+  constructor of the simulator.
+* ``mockturtle::partial_simulator``: This simulator simulates partial truth tables,
+  whose length is flexible and new simulation patterns can be added.

docs/techmap.rst

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+Techmap
+=============
+
+**Header:** ``mockturtle/algorithms/mapper.hpp``
+
+A versatile mapper that supports technology mapping and graph mapping
+(optimized network conversion). The mapper is independent of the
+underlying graph representation. Hence, it supports generic subject
+graph representations (e.g., AIG, and MIG) and a generic target
+representation (e.g. cell library, XMG). The mapper aims at finding a
+good mapping with respect to delay, area, and switching power.
+
+The mapper uses a library (hash table) to facilitate Boolean matching.
+For technology mapping, it needs `tech_library` while for graph mapping
+it needs `exact_library`. For technology mapping, the generation of both NP- and
+P-configurations of gates are supported. Generally, it is convenient to use
+NP-configurations for small or medium size cell libraries. For bigger libraries,
+P-configurations should perform better. You can test both the configurations to
+see which one has the best run time. For graph mapping, NPN classification
+is used instead.

docs/write.rst

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+Write into file formats
+-----------------------
+
+Write into AIGER files
+~~~~~~~~~~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/io/write_aiger.hpp``
+
+Writes a combinational AIG network in binary AIGER format into a file.
+
+This function should be only called on “clean” aig_networks.
+
+Write into BENCH files
+~~~~~~~~~~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/io/write_bench.hpp``
+
+Writes network in BENCH format into a file.
+
+Write into BLIF files
+~~~~~~~~~~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/io/write_blif.hpp``
+
+Writes network in BLIF format into a file.
+
+Write into structural Verilog files
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/io/write_verilog.hpp``
+
+Writes network in structural Verilog format into a file.
+
+Write into DIMACS files (CNF)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/io/write_cnf.hpp``
+
+Writes network into CNF DIMACS format.
+
+It also adds unit clauses for the outputs. Therefore a satisfying solution is one that makes all outputs 1.
+
+.. _write_dot:
+
+Write into DOT files (Graphviz)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/io/write_dot.hpp``
+
+Writes network in DOT format into a file.