PigMAP update
parent
63c125a1fa
commit
2499d94260
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@ -159,7 +159,7 @@ class techmap_command : public command {
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st.total_wirelength);
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st.total_wirelength);
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} else {
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} else {
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auto res = mockturtle::map(aig, lib, ps, &st);
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auto res = mockturtle::map(aig, lib, ps, &st);
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if (is_set("output")) write_verilog_with_binding_new(res, filename);
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if (is_set("output")) write_verilog_with_binding(res, filename);
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std::cout << fmt::format(
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std::cout << fmt::format(
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"Mapped AIG into #gates = {}, area = {:.2f}, delay = {:.2f}, "
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"Mapped AIG into #gates = {}, area = {:.2f}, delay = {:.2f}, "
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"power = {:.2f}\n",
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"power = {:.2f}\n",
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