2022-12-21 08:45:50 +00:00
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Examples
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============
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2023-02-05 10:43:14 +00:00
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All commands
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2022-12-21 08:45:50 +00:00
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----------------------------------
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2023-02-05 10:43:14 +00:00
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Input:
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2023-02-05 11:00:49 +00:00
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::
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2023-02-05 10:43:14 +00:00
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help
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2022-12-21 08:45:50 +00:00
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2023-02-05 11:00:49 +00:00
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2023-02-05 10:43:14 +00:00
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Output:
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::
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Verification commands:
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cec exprsim sat sim
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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Mapping commands:
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lut_mapping lutmap techmap
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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Synthesis commands:
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balance create_graph reduction refactor
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resub resyn rewrite
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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I/O commands:
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load read_aiger read_bench read_blif
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read_genlib read_verilog write_aiger write_bench
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write_blif write_dot write_genlib write_verilog
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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General commands:
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alias convert current help
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print ps quit set
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show store
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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For more details, simply add '-h' after command to see all options of this command.
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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Synthesis of EPFL benchmarks
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----------------------------------
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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In the following example, we show how `phyLS` can be used to synthesize a EPFL benchamrk.
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2022-12-21 08:45:50 +00:00
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2023-02-05 10:43:14 +00:00
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Input:
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2023-02-05 11:00:49 +00:00
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::
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2023-02-05 10:43:14 +00:00
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read_aiger ~/phyLS/benchmarks/adder.aig
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ps -a
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resub // any synthesis commands
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ps -a
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read_genlib ~/phyLS/src/mcnc.genlib
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techmap
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Output:
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::
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$ AIG i/o = 256/129 gates = 1020 level = 255
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$ ntk i/o = 256/129 gates = 893 level = 256
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[CPU time] 0.09 s
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$ Mapped AIG into #gates = 701 area = 1849.00 delay = 204.90
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