phyLS/docs/examples.rst

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Examples
============
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All commands
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----------------
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Input:
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::
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help
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Output:
::
Verification commands:
cec exprsim sat sim
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Mapping commands:
lut_mapping lutmap techmap
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Synthesis commands:
balance create_graph reduction refactor
resub resyn rewrite
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I/O commands:
load read_aiger read_bench read_blif
read_genlib read_verilog write_aiger write_bench
write_blif write_dot write_genlib write_verilog
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General commands:
alias convert current help
print ps quit set
show store
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For more details, simply add '-h' after command to see all options of this command.
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Synthesis of EPFL benchmarks
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----------------
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In the following example, we show how `phyLS` can be used to synthesize a EPFL benchamrk.
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Input:
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::
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read_aiger ~/phyLS/benchmarks/adder.aig
ps -a
resub // any synthesis commands
ps -a
read_genlib ~/phyLS/src/mcnc.genlib
techmap
Output:
::
$ AIG i/o = 256/129 gates = 1020 level = 255
$ ntk i/o = 256/129 gates = 893 level = 256
[CPU time] 0.09 s
$ Mapped AIG into #gates = 701 area = 1849.00 delay = 204.90