2022-12-21 08:45:50 +00:00
|
|
|
Examples
|
|
|
|
|
============
|
|
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
All commands
|
2023-02-06 05:29:42 +00:00
|
|
|
----------------
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Input:
|
2023-02-05 11:00:49 +00:00
|
|
|
::
|
2023-02-05 10:43:14 +00:00
|
|
|
help
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 11:00:49 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Output:
|
|
|
|
|
::
|
2023-08-03 02:03:27 +00:00
|
|
|
ABC commands:
|
|
|
|
|
aresub comb fraig strash
|
|
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Verification commands:
|
2023-08-03 02:03:27 +00:00
|
|
|
acec cec exprsim sat
|
|
|
|
|
sim simulator
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Mapping commands:
|
|
|
|
|
lut_mapping lutmap techmap
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Synthesis commands:
|
2023-08-03 02:03:27 +00:00
|
|
|
balance create_graph exact fr
|
|
|
|
|
lutrw refactor resub resyn
|
|
|
|
|
rewrite stpfr
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
I/O commands:
|
2023-08-03 02:03:27 +00:00
|
|
|
load read read_aiger read_bench
|
|
|
|
|
read_blif read_genlib read_gia read_verilog
|
|
|
|
|
write write_aiger write_bench write_blif
|
|
|
|
|
write_dot write_genlib write_gia write_verilog
|
|
|
|
|
|
|
|
|
|
Gia commands:
|
|
|
|
|
Afraig Aget
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
General commands:
|
|
|
|
|
alias convert current help
|
|
|
|
|
print ps quit set
|
|
|
|
|
show store
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
For more details, simply add '-h' after command to see all options of this command.
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Synthesis of EPFL benchmarks
|
2023-02-06 05:29:42 +00:00
|
|
|
----------------
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
In the following example, we show how `phyLS` can be used to synthesize a EPFL benchamrk.
|
2022-12-21 08:45:50 +00:00
|
|
|
|
2023-02-05 10:43:14 +00:00
|
|
|
Input:
|
2023-02-05 11:00:49 +00:00
|
|
|
::
|
2023-02-05 10:43:14 +00:00
|
|
|
read_aiger ~/phyLS/benchmarks/adder.aig
|
|
|
|
|
ps -a
|
|
|
|
|
resub // any synthesis commands
|
|
|
|
|
ps -a
|
|
|
|
|
read_genlib ~/phyLS/src/mcnc.genlib
|
|
|
|
|
techmap
|
|
|
|
|
|
|
|
|
|
Output:
|
|
|
|
|
::
|
|
|
|
|
$ AIG i/o = 256/129 gates = 1020 level = 255
|
|
|
|
|
$ ntk i/o = 256/129 gates = 893 level = 256
|
|
|
|
|
[CPU time] 0.09 s
|
|
|
|
|
$ Mapped AIG into #gates = 701 area = 1849.00 delay = 204.90
|
