122 lines
4.8 KiB
C
122 lines
4.8 KiB
C
/******************************************************************************
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Copyright (C), 2001-2011, Hisilicon Tech. Co., Ltd.
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******************************************************************************
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File Name : hi_vreg.h
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Version : Initial Draft
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Author : Hisilicon multimedia software group
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Created : 2013/01/09
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Description :
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History :
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1.Date : 2013/01/09
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Author : n00168968
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Modification: Created file
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******************************************************************************/
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#ifndef __HI_VREG_H__
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#define __HI_VREG_H__
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#include "hi_type.h"
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#include "hi_comm_isp.h"
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#ifdef __cplusplus
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#if __cplusplus
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extern "C"{
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#endif
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#endif /* End of #ifdef __cplusplus */
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#define REG_ACCESS_WIDTH_1 0
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#define REG_ACCESS_WIDTH 0 /* 1: 16bit 2: 8bit */
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/* Vreg is a blok of memory alloced to simulate the regs.
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* We try to differentiate vregs by baseaddr. Each vreg
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* block's size should at least 4k bytes.
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*/
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/*---------------------------------------------------------------------------------------------------------*
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*| 0x205A0000 | 0x10000 | 0x20000 | 0x21000 | ... | 0x30000 | ... | 0x40000 | ... | 0x80000 | ...|*
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*|------------|-----------|----------|----------|-----|-----------|-----|----------|-----|----------|----|*
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*| ISP_REG | ISP_VREG | AE1_VREG | AE2_VREG | ... | AWB1_VREG | ... | AF1_VREG | ... | VIU_VREG | ...|*
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*---------------------------------------------------------------------------------------------------------*/
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#define ISP_REG_BASE 0x205A0000
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#define ISP_REG_SIZE 0x1ffff
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#define VI_REG_BASE 0x20580000
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#define VI_REG_SIZE 0x20000
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#define VREG_SIZE_ALIGN 0x1000
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#define EXT_REG_BASE 0x10000
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#define ISP_VREG_BASE 0x10000
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#define ISP_VREG_SIZE (VREG_SIZE_ALIGN << 4)
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#define AE_LIB_VREG_BASE(id) (0x20000 + VREG_SIZE_ALIGN * (id))
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#define AWB_LIB_VREG_BASE(id) (0x30000 + VREG_SIZE_ALIGN * (id))
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#define AF_LIB_VREG_BASE(id) (0x40000 + VREG_SIZE_ALIGN * (id))
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#define ALG_LIB_VREG_SIZE (VREG_SIZE_ALIGN)
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#define MAX_ALG_LIB_VREG_NUM (1 << 4)
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#define HISI_AE_LIB_EXTREG_ID_0 0
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#define HISI_AE_LIB_EXTREG_ID_1 1
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#define HISI_AWB_LIB_EXTREG_ID_0 0
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#define HISI_AWB_LIB_EXTREG_ID_1 1
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#define VIU_VREG_BASE 0x80000
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#define VPP_VREG_BASE 0x90000
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#define VEDU_VREG_BASE 0xa0000
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#define VOU_VREG_BASE 0xb0000
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HI_S32 VReg_Init(HI_U32 u32BaseAddr, HI_U32 u32Size);
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HI_S32 VReg_Exit(HI_U32 u32BaseAddr, HI_U32 u32Size);
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HI_U32 VReg_GetVirtAddr(HI_U32 u32BaseAddr);
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HI_VOID VReg_Munmap(HI_VOID);
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HI_U32 IO_READ32(HI_U32 u32Addr);
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HI_S32 IO_WRITE32(HI_U32 u32Addr, HI_U32 u32Value);
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HI_U16 IO_READ16(HI_U32 u32Addr);
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HI_S32 IO_WRITE16(HI_U32 u32Addr, HI_U32 u32Value);
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HI_U8 IO_READ8(HI_U32 u32Addr);
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HI_S32 IO_WRITE8(HI_U32 u32Addr, HI_U32 u32Value);
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/* Dynamic bus access functions, 4 byte align access */
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//TODO: allocate dev addr (such as ISP_REG_BASE_ADDR) according to devId.
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#define __IO_CALC_ADDRESS_DYNAMIC(BASE) (HI_U32)(((BASE >= (EXT_REG_BASE)) ? 0 : ISP_REG_BASE) + (BASE))
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#define IORD_32DIRECT(BASE) IO_READ32(__IO_CALC_ADDRESS_DYNAMIC(BASE))
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#define IORD_16DIRECT(BASE) IO_READ16(__IO_CALC_ADDRESS_DYNAMIC(BASE))
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#define IORD_8DIRECT(BASE) IO_READ8(__IO_CALC_ADDRESS_DYNAMIC(BASE))
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#define IOWR_32DIRECT(BASE, DATA) IO_WRITE32(__IO_CALC_ADDRESS_DYNAMIC(BASE), (DATA))
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#define IOWR_16DIRECT(BASE, DATA) IO_WRITE16(__IO_CALC_ADDRESS_DYNAMIC(BASE), (DATA))
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#define IOWR_8DIRECT(BASE, DATA) IO_WRITE8(__IO_CALC_ADDRESS_DYNAMIC(BASE), (DATA))
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/*--------------------------------------------------------------------------------------*/
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/* direct write or read ISP regs */
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#define IORD_32DIRECT_ISP_REG(BASE) IO_READ32(ISP_REG_BASE + (BASE))
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#define IORD_16DIRECT_ISP_REG(BASE) IO_READ16(ISP_REG_BASE + (BASE))
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#define IORD_8DIRECT_ISP_REG(BASE) IO_READ8(ISP_REG_BASE + (BASE))
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#define IOWR_32DIRECT_ISP_REG(BASE, DATA) IO_WRITE32((ISP_REG_BASE + (BASE)), (DATA))
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#define IOWR_16DIRECT_ISP_REG(BASE, DATA) IO_WRITE16((ISP_REG_BASE + (BASE)), (DATA))
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#define IOWR_8DIRECT_ISP_REG(BASE, DATA) IO_WRITE8((ISP_REG_BASE + (BASE)), (DATA))
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/*--------------------------------------------------------------------------------------*/
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/* write or read vi reg */
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HI_U32 IO_READ32_VI(HI_U32 u32Addr);
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HI_S32 IO_WRITE32_VI(HI_U32 u32Addr, HI_U32 u32Value);
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#define __IO_CALC_ADDRESS_DYNAMIC_VI(BASE) (HI_U32)((VI_REG_BASE) + (BASE))
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#define IORD_32DIRECT_VI(BASE) IO_READ32_VI(__IO_CALC_ADDRESS_DYNAMIC_VI(BASE))
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#define IOWR_32DIRECT_VI(BASE, DATA) IO_WRITE32_VI(__IO_CALC_ADDRESS_DYNAMIC_VI(BASE), (DATA))
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/*--------------------------------------------------------------------------------------*/
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#ifdef __cplusplus
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#if __cplusplus
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}
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#endif
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#endif /* End of #ifdef __cplusplus */
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#endif
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