257 lines
7.8 KiB
C
257 lines
7.8 KiB
C
#ifndef __HI_MIPI__
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#define __HI_MIPI__
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#include "hi_type.h"
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typedef unsigned int MIPI_PHY;
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typedef unsigned int COMBO_LINK;
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#define LVDS_MIN_WIDTH 32
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#define LVDS_MIN_HEIGHT 32
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#define COMBO_MAX_LINK_NUM 2 /* hi3518ev200 has 1 links, For compatibility of Hi3516A, use 2 */
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#define COMBO_MAX_LANE_NUM 8
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#define LANE_NUM_PER_LINK 4 /* one link has 4 lanes */
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#define MIPI_LANE_NUM COMBO_MAX_LANE_NUM /* hi3518ev200 support 1 link mipi only, For compatibility of Hi3516A, use 2*/
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#define LVDS_LANE_NUM COMBO_MAX_LANE_NUM /* hi3518ev200 has 1 links, so has 4 lanes. For compatibility of Hi3516A, use 8 */
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#define WDR_VC_NUM 4
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#define SYNC_CODE_NUM 4
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/* int mask */
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#define COMBO_LINK_INT_DEF (0x00200000)
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#define COMBO_LINK_INT_MASK (0x300000)
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//~(COMBO_LINK_INT_DEF) /* 0: enable int */
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#define MIPI_INT1_INT_DEF (0x1000fff0)
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//#define MIPI_INT1_MASK ~(MIPI_INT1_INT_DEF) /* 0: enable int */
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#define MIPI_INT2_INT_DEF (0xf000)
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//#define MIPI_INT2_MASK ~(MIPI_INT2_INT_DEF) /* 0: enable int */
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#define MIPI_INT_MASK 0x0
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//#define HI_MIPI_REG_DEBUG
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//#define HI_MIPI_DEBUG
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#ifdef HI_MIPI_DEBUG
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#define HI_MSG(x...) \
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do { \
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printk("%s->%d: ", __FUNCTION__, __LINE__); \
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printk(x); \
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printk("\n"); \
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} while (0)
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#else
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#define HI_MSG(args...) do { } while (0)
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#endif
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#define HI_ERR(x...) \
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do { \
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printk(KERN_ALERT "%s(%d): ", __FUNCTION__, __LINE__); \
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printk(KERN_ALERT x); \
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printk(KERN_ALERT "\n"); \
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} while (0)
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typedef enum
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{
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MIPI_VC0_NO_MATCH = 0x1 << 4, /*VC0通道的帧起始和帧结束不匹配*/
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MIPI_VC1_NO_MATCH = 0x1 << 5, /*VC1通道的帧起始和帧结束不匹配*/
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MIPI_VC2_NO_MATCH = 0x1 << 6, /*VC2通道的帧起始和帧结束不匹配*/
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MIPI_VC3_NO_MATCH = 0x1 << 7, /*VC3通道的帧起始和帧结束不匹配*/
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MIPI_VC0_ORDER_ERR = 0x1 << 8, /*VC0的帧序出错*/
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MIPI_VC1_ORDER_ERR = 0x1 << 9, /*VC1的帧序出错*/
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MIPI_VC2_ORDER_ERR = 0x1 << 10, /*VC2的帧序出错*/
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MIPI_VC3_ORDER_ERR = 0x1 << 11, /*VC3的帧序出错*/
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MIPI_VC0_FRAME_CRC = 0x1 << 12, /*最后一帧数据中，VC0通道数据至少有一个CRC错误*/
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MIPI_VC1_FRAME_CRC = 0x1 << 13, /*最后一帧数据中，VC1通道数据至少有一个CRC错误*/
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MIPI_VC2_FRAME_CRC = 0x1 << 14, /*最后一帧数据中，VC2通道数据至少有一个CRC错误*/
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MIPI_VC3_FRAME_CRC = 0x1 << 15, /*最后一帧数据中，VC3通道数据至少有一个CRC错误*/
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MIPI_HEADER_ERR = 0x1 << 28, /*Header至少2个错误，ECC无法纠错*/
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}MIPI_INT_ERR;
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typedef enum
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{
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MIPI_VC0_INVALID_DT = 0x1 << 12, /*VC0通道数据类型不支持*/
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MIPI_VC1_INVALID_DT = 0x1 << 13, /*VC1通道数据类型不支持*/
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MIPI_VC2_INVALID_DT = 0x1 << 14, /*VC2通道数据类型不支持*/
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MIPI_VC3_INVALID_DT = 0x1 << 15, /*VC3通道数据类型不支持*/
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}MIPI_INT2_ERR;
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typedef enum
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{
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MIPI_ESC_CLK = 0x1 << 0, /*MIPI模式时Link 0 clock lane escape序列中断状态。*/
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MIPI_ESC_D0 = 0x1 << 1, /*data lane 0 escape序列中断状态*/
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MIPI_ESC_D1 = 0x1 << 2, /*data lane 1 escape序列中断状态*/
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MIPI_ESC_D2 = 0x1 << 3, /*data lane 2 escape序列中断状态*/
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MIPI_ESC_D3 = 0x1 << 4, /*data lane 3 escape序列中断状态*/
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MIPI_TIMEOUT_CLK = 0x1 << 8, /*clock lane FSM timeout 中断状态*/
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MIPI_TIMEOUT_D0 = 0x1 << 9, /*data lane 0 FSM timeout 中断状态*/
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MIPI_TIMEOUT_D1 = 0x1 << 10, /*data lane 1 FSM timeout 中断状态*/
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MIPI_TIMEOUT_D2 = 0x1 << 11, /*data lane 2 FSM timeout 中断状态*/
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MIPI_TIMEOUT_D3 = 0x1 << 12, /*data lane 3 FSM timeout 中断状态*/
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MIPI_VSYNC_ERR = 0x1 << 21, /* LVDS模式，Link 0 各个lane 帧同步信号vsync有效不同步中断状态。*/
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}LINK_INT_STAT;
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typedef enum
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{
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LANE0_SYNC_ERR = 0x1,
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LANE1_SYNC_ERR = 0x2,
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LANE2_SYNC_ERR = 0x4,
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LANE3_SYNC_ERR = 0x8,
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LANE4_SYNC_ERR = 0x10,
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LANE5_SYNC_ERR = 0x20,
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LANE6_SYNC_ERR = 0x40,
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LANE7_SYNC_ERR = 0x80,
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PHY0_LINE_SYNC_ERR = 0x100,
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PHY0_FRAME_SYNC_ERR = 0x200,
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PHY1_LINE_SYNC_ERR = 0x400,
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PHY1_FRAME_SYNC_ERR = 0x800,
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LINK_SYNC_ERR = 0x3F0000, /* link的行/帧结束信号无法正常检测中断状态，如果有此中断则要重启link。*/
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}LVDS_SYNC_INTR_ERR;
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typedef enum
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{
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OUTPUT_DATA_WIDTH_2BIT=0,
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OUTPUT_DATA_WIDTH_4BIT,
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OUTPUT_DATA_WIDTH_8BIT,
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OUTPUT_DATA_WIDTH_BUTT
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}output_data_width;
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typedef enum
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{
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CLK_UP_EDGE=0,
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CLK_DOWN_EDGE,
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CLK_EDGE_BUTT
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}clk_edge;
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typedef enum
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{
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OUTPUT_NORM_MSB=0,
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OUTPUT_REVERSE_MSB,
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OUTPUT_MSB_BUTT
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}output_msb;
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typedef enum
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{
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INPUT_MODE_MIPI = 0x0, /* mipi */
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INPUT_MODE_SUBLVDS = 0x1, /* SUB_LVDS */
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INPUT_MODE_LVDS = 0x2, /* LVDS */
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INPUT_MODE_HISPI = 0x3, /* HISPI */
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INPUT_MODE_CMOS_18V = 0x4, /* CMOS 1.8V */
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INPUT_MODE_CMOS_33V = 0x5, /* CMOS 3.3V */
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INPUT_MODE_BT1120 = 0x6, /* CMOS 3.3V */
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INPUT_MODE_BYPASS = 0x7, /* MIPI Bypass */
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INPUT_MODE_BUTT
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}input_mode_t;
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typedef enum
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{
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WORK_MODE_LVDS = 0x0,
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WORK_MODE_MIPI = 0x1,
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WORK_MODE_CMOS_18V = 0x2,
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WORK_MODE_CMOS_33V = 0x4,
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WORK_MODE_BT1120 = 0x4,
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WORK_MODE_BUTT
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}work_mode_t;
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typedef struct
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{
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unsigned int width;
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unsigned int height;
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}img_size_t;
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typedef enum
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{
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HI_WDR_MODE_NONE = 0x0,
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HI_WDR_MODE_2F = 0x1,
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HI_WDR_MODE_3F = 0x2,
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HI_WDR_MODE_4F = 0x3,
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HI_WDR_MODE_DOL_2F = 0x4,
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HI_WDR_MODE_DOL_3F = 0x5,
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HI_WDR_MODE_DOL_4F = 0x6,
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HI_WDR_MODE_BUTT
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}wdr_mode_e;
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typedef enum
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{
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LVDS_ENDIAN_LITTLE = 0x0,
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LVDS_ENDIAN_BIG = 0x1,
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LVDS_ENDIAN_BUTT
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}lvds_bit_endian;
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typedef enum
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{
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LVDS_SYNC_MODE_SOL = 0, /* sensor SOL, EOL, SOF, EOF */
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LVDS_SYNC_MODE_SAV, /* SAV, EAV */
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LVDS_SYNC_MODE_BUTT
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}lvds_sync_mode_e;
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typedef enum
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{
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RAW_DATA_8BIT = 1,
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RAW_DATA_10BIT,
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RAW_DATA_12BIT,
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RAW_DATA_14BIT,
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RAW_DATA_BUTT
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}raw_data_type_e;
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typedef struct
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{
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img_size_t img_size; /* oringnal sensor input image size */
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wdr_mode_e wdr_mode; /* WDR mode */
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lvds_sync_mode_e sync_mode; /* sync mode: SOL, SAV */
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raw_data_type_e raw_data_type; /* raw data type: 8/10/12/14 bit */
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lvds_bit_endian data_endian; /* data endian: little/big */
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lvds_bit_endian sync_code_endian; /* sync code endian: little/big */
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short lane_id[LVDS_LANE_NUM]; /* lane_id: -1 - disable */
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/* each vc has 4 params, sync_code[i]:
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sync_mode is SYNC_MODE_SOL: SOL, EOL, SOF, EOF
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sync_mode is SYNC_MODE_SAV: valid sav, valid eav, invalid sav, invalid eav */
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unsigned short sync_code[LVDS_LANE_NUM][WDR_VC_NUM][SYNC_CODE_NUM];
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}lvds_dev_attr_t;
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typedef struct
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{
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raw_data_type_e raw_data_type; /* raw data type: 8/10/12/14 bit */
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short lane_id[MIPI_LANE_NUM]; /* lane_id: -1 - disable */
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}mipi_dev_attr_t;
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typedef struct
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{
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input_mode_t input_mode; /* input mode: MIPI/LVDS/SUBLVDS/HISPI/DC */
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union
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{
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mipi_dev_attr_t mipi_attr;
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lvds_dev_attr_t lvds_attr;
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};
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}combo_dev_attr_t;
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#define HI_MIPI_IOC_MAGIC 'm'
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/* init data lane, input mode, data type */
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#define HI_MIPI_SET_DEV_ATTR _IOW(HI_MIPI_IOC_MAGIC, 0x01, combo_dev_attr_t)
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/* output clk edge */
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#define HI_MIPI_SET_OUTPUT_CLK_EDGE _IOW(HI_MIPI_IOC_MAGIC, 0x02, HI_BOOL)
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/* output data msb */
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#define HI_MIPI_SET_OUTPUT_MSB _IOW(HI_MIPI_IOC_MAGIC, 0x03, HI_BOOL)
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#endif
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