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multimedia/device/mpp/include/hi_mipi.h

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添加3518 开发板 例子代码 用于二次开发
2019-09-09 17:17:53 +00:00
#ifndef __HI_MIPI__
#define __HI_MIPI__
#include "hi_type.h"
typedef unsigned int MIPI_PHY;
typedef unsigned int COMBO_LINK;
#define LVDS_MIN_WIDTH 32
#define LVDS_MIN_HEIGHT 32
#define COMBO_MAX_LINK_NUM 2 /* hi3518ev200 has 1 links, For compatibility of Hi3516A, use 2 */
#define COMBO_MAX_LANE_NUM 8
#define LANE_NUM_PER_LINK 4 /* one link has 4 lanes */
#define MIPI_LANE_NUM COMBO_MAX_LANE_NUM /* hi3518ev200 support 1 link mipi only, For compatibility of Hi3516A, use 2*/
#define LVDS_LANE_NUM COMBO_MAX_LANE_NUM /* hi3518ev200 has 1 links, so has 4 lanes. For compatibility of Hi3516A, use 8 */
#define WDR_VC_NUM 4
#define SYNC_CODE_NUM 4
/* int mask */
#define COMBO_LINK_INT_DEF (0x00200000)
#define COMBO_LINK_INT_MASK (0x300000)
//~(COMBO_LINK_INT_DEF) /* 0: enable int */
#define MIPI_INT1_INT_DEF (0x1000fff0)
//#define MIPI_INT1_MASK ~(MIPI_INT1_INT_DEF) /* 0: enable int */
#define MIPI_INT2_INT_DEF (0xf000)
//#define MIPI_INT2_MASK ~(MIPI_INT2_INT_DEF) /* 0: enable int */
#define MIPI_INT_MASK 0x0
//#define HI_MIPI_REG_DEBUG
//#define HI_MIPI_DEBUG
#ifdef HI_MIPI_DEBUG
#define HI_MSG(x...) \
do { \
printk("%s->%d: ", __FUNCTION__, __LINE__); \
printk(x); \
printk("\n"); \
} while (0)
#else
#define HI_MSG(args...) do { } while (0)
#endif
#define HI_ERR(x...) \
do { \
printk(KERN_ALERT "%s(%d): ", __FUNCTION__, __LINE__); \
printk(KERN_ALERT x); \
printk(KERN_ALERT "\n"); \
} while (0)
typedef enum
{
MIPI_VC0_NO_MATCH = 0x1 << 4, /*VC0ͨ<30><CDA8><EFBFBD><EFBFBD>֡<EFBFBD><D6A1>ʼ<EFBFBD><CABC>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƥ<EFBFBD><C6A5>*/
MIPI_VC1_NO_MATCH = 0x1 << 5, /*VC1ͨ<31><CDA8><EFBFBD><EFBFBD>֡<EFBFBD><D6A1>ʼ<EFBFBD><CABC>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƥ<EFBFBD><C6A5>*/
MIPI_VC2_NO_MATCH = 0x1 << 6, /*VC2ͨ<32><CDA8><EFBFBD><EFBFBD>֡<EFBFBD><D6A1>ʼ<EFBFBD><CABC>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƥ<EFBFBD><C6A5>*/
MIPI_VC3_NO_MATCH = 0x1 << 7, /*VC3ͨ<33><CDA8><EFBFBD><EFBFBD>֡<EFBFBD><D6A1>ʼ<EFBFBD><CABC>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƥ<EFBFBD><C6A5>*/
MIPI_VC0_ORDER_ERR = 0x1 << 8, /*VC0<43><30>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
MIPI_VC1_ORDER_ERR = 0x1 << 9, /*VC1<43><31>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
MIPI_VC2_ORDER_ERR = 0x1 << 10, /*VC2<43><32>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
MIPI_VC3_ORDER_ERR = 0x1 << 11, /*VC3<43><33>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
MIPI_VC0_FRAME_CRC = 0x1 << 12, /*<2A><><EFBFBD><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>VC0ͨ<30><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>CRC<52><43><EFBFBD><EFBFBD>*/
MIPI_VC1_FRAME_CRC = 0x1 << 13, /*<2A><><EFBFBD><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>VC1ͨ<31><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>CRC<52><43><EFBFBD><EFBFBD>*/
MIPI_VC2_FRAME_CRC = 0x1 << 14, /*<2A><><EFBFBD><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>VC2ͨ<32><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>CRC<52><43><EFBFBD><EFBFBD>*/
MIPI_VC3_FRAME_CRC = 0x1 << 15, /*<2A><><EFBFBD><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>VC3ͨ<33><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>CRC<52><43><EFBFBD><EFBFBD>*/
MIPI_HEADER_ERR = 0x1 << 28, /*Header<65><72><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ECC<43>޷<EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD>*/
}MIPI_INT_ERR;
typedef enum
{
MIPI_VC0_INVALID_DT = 0x1 << 12, /*VC0ͨ<30><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD>֧<EFBFBD><D6A7>*/
MIPI_VC1_INVALID_DT = 0x1 << 13, /*VC1ͨ<31><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD>֧<EFBFBD><D6A7>*/
MIPI_VC2_INVALID_DT = 0x1 << 14, /*VC2ͨ<32><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD>֧<EFBFBD><D6A7>*/
MIPI_VC3_INVALID_DT = 0x1 << 15, /*VC3ͨ<33><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD>֧<EFBFBD><D6A7>*/
}MIPI_INT2_ERR;
typedef enum
{
MIPI_ESC_CLK = 0x1 << 0, /*MIPIģʽʱLink 0 clock lane escape<70><65><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬<D7B4><CCAC>*/
MIPI_ESC_D0 = 0x1 << 1, /*data lane 0 escape<70><65><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬*/
MIPI_ESC_D1 = 0x1 << 2, /*data lane 1 escape<70><65><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬*/
MIPI_ESC_D2 = 0x1 << 3, /*data lane 2 escape<70><65><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬*/
MIPI_ESC_D3 = 0x1 << 4, /*data lane 3 escape<70><65><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬*/
MIPI_TIMEOUT_CLK = 0x1 << 8, /*clock lane FSM timeout <20>ж<EFBFBD>״̬*/
MIPI_TIMEOUT_D0 = 0x1 << 9, /*data lane 0 FSM timeout <20>ж<EFBFBD>״̬*/
MIPI_TIMEOUT_D1 = 0x1 << 10, /*data lane 1 FSM timeout <20>ж<EFBFBD>״̬*/
MIPI_TIMEOUT_D2 = 0x1 << 11, /*data lane 2 FSM timeout <20>ж<EFBFBD>״̬*/
MIPI_TIMEOUT_D3 = 0x1 << 12, /*data lane 3 FSM timeout <20>ж<EFBFBD>״̬*/
MIPI_VSYNC_ERR = 0x1 << 21, /* LVDSģʽ<C4A3><CABD>Link 0 <20><><EFBFBD><EFBFBD>lane ֡ͬ<D6A1><CDAC><EFBFBD>ź<EFBFBD>vsync<6E><63>Ч<EFBFBD><D0A7>ͬ<EFBFBD><CDAC><EFBFBD>ж<EFBFBD>״̬<D7B4><CCAC>*/
}LINK_INT_STAT;
typedef enum
{
LANE0_SYNC_ERR = 0x1,
LANE1_SYNC_ERR = 0x2,
LANE2_SYNC_ERR = 0x4,
LANE3_SYNC_ERR = 0x8,
LANE4_SYNC_ERR = 0x10,
LANE5_SYNC_ERR = 0x20,
LANE6_SYNC_ERR = 0x40,
LANE7_SYNC_ERR = 0x80,
PHY0_LINE_SYNC_ERR = 0x100,
PHY0_FRAME_SYNC_ERR = 0x200,
PHY1_LINE_SYNC_ERR = 0x400,
PHY1_FRAME_SYNC_ERR = 0x800,
LINK_SYNC_ERR = 0x3F0000, /* link<6E><6B><EFBFBD><EFBFBD>/֡<><D6A1><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD><C5BA>޷<EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ж<EFBFBD><D0B6><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>link<6E><6B>*/
}LVDS_SYNC_INTR_ERR;
typedef enum
{
OUTPUT_DATA_WIDTH_2BIT=0,
OUTPUT_DATA_WIDTH_4BIT,
OUTPUT_DATA_WIDTH_8BIT,
OUTPUT_DATA_WIDTH_BUTT
}output_data_width;
typedef enum
{
CLK_UP_EDGE=0,
CLK_DOWN_EDGE,
CLK_EDGE_BUTT
}clk_edge;
typedef enum
{
OUTPUT_NORM_MSB=0,
OUTPUT_REVERSE_MSB,
OUTPUT_MSB_BUTT
}output_msb;
typedef enum
{
INPUT_MODE_MIPI = 0x0, /* mipi */
INPUT_MODE_SUBLVDS = 0x1, /* SUB_LVDS */
INPUT_MODE_LVDS = 0x2, /* LVDS */
INPUT_MODE_HISPI = 0x3, /* HISPI */
INPUT_MODE_CMOS_18V = 0x4, /* CMOS 1.8V */
INPUT_MODE_CMOS_33V = 0x5, /* CMOS 3.3V */
INPUT_MODE_BT1120 = 0x6, /* CMOS 3.3V */
INPUT_MODE_BYPASS = 0x7, /* MIPI Bypass */
INPUT_MODE_BUTT
}input_mode_t;
typedef enum
{
WORK_MODE_LVDS = 0x0,
WORK_MODE_MIPI = 0x1,
WORK_MODE_CMOS_18V = 0x2,
WORK_MODE_CMOS_33V = 0x4,
WORK_MODE_BT1120 = 0x4,
WORK_MODE_BUTT
}work_mode_t;
typedef struct
{
unsigned int width;
unsigned int height;
}img_size_t;
typedef enum
{
HI_WDR_MODE_NONE = 0x0,
HI_WDR_MODE_2F = 0x1,
HI_WDR_MODE_3F = 0x2,
HI_WDR_MODE_4F = 0x3,
HI_WDR_MODE_DOL_2F = 0x4,
HI_WDR_MODE_DOL_3F = 0x5,
HI_WDR_MODE_DOL_4F = 0x6,
HI_WDR_MODE_BUTT
}wdr_mode_e;
typedef enum
{
LVDS_ENDIAN_LITTLE = 0x0,
LVDS_ENDIAN_BIG = 0x1,
LVDS_ENDIAN_BUTT
}lvds_bit_endian;
typedef enum
{
LVDS_SYNC_MODE_SOL = 0, /* sensor SOL, EOL, SOF, EOF */
LVDS_SYNC_MODE_SAV, /* SAV, EAV */
LVDS_SYNC_MODE_BUTT
}lvds_sync_mode_e;
typedef enum
{
RAW_DATA_8BIT = 1,
RAW_DATA_10BIT,
RAW_DATA_12BIT,
RAW_DATA_14BIT,
RAW_DATA_BUTT
}raw_data_type_e;
typedef struct
{
img_size_t img_size; /* oringnal sensor input image size */
wdr_mode_e wdr_mode; /* WDR mode */
lvds_sync_mode_e sync_mode; /* sync mode: SOL, SAV */
raw_data_type_e raw_data_type; /* raw data type: 8/10/12/14 bit */
lvds_bit_endian data_endian; /* data endian: little/big */
lvds_bit_endian sync_code_endian; /* sync code endian: little/big */
short lane_id[LVDS_LANE_NUM]; /* lane_id: -1 - disable */
/* each vc has 4 params, sync_code[i]:
sync_mode is SYNC_MODE_SOL: SOL, EOL, SOF, EOF
sync_mode is SYNC_MODE_SAV: valid sav, valid eav, invalid sav, invalid eav */
unsigned short sync_code[LVDS_LANE_NUM][WDR_VC_NUM][SYNC_CODE_NUM];
}lvds_dev_attr_t;
typedef struct
{
raw_data_type_e raw_data_type; /* raw data type: 8/10/12/14 bit */
short lane_id[MIPI_LANE_NUM]; /* lane_id: -1 - disable */
}mipi_dev_attr_t;
typedef struct
{
input_mode_t input_mode; /* input mode: MIPI/LVDS/SUBLVDS/HISPI/DC */
union
{
mipi_dev_attr_t mipi_attr;
lvds_dev_attr_t lvds_attr;
};
}combo_dev_attr_t;
#define HI_MIPI_IOC_MAGIC 'm'
/* init data lane, input mode, data type */
#define HI_MIPI_SET_DEV_ATTR _IOW(HI_MIPI_IOC_MAGIC, 0x01, combo_dev_attr_t)
/* output clk edge */
#define HI_MIPI_SET_OUTPUT_CLK_EDGE _IOW(HI_MIPI_IOC_MAGIC, 0x02, HI_BOOL)
/* output data msb */
#define HI_MIPI_SET_OUTPUT_MSB _IOW(HI_MIPI_IOC_MAGIC, 0x03, HI_BOOL)
#endif