`timescale 1ns / 1ps

module simu(
);
    reg clk = 0;
    reg adcclk = 0;
    
    reg reset = 1;
    
    // Κδ³φΠΕΊΕ
    wire [31:0]data;
    wire tvalid;
    wire [3:0]tstrd;
    wire tlast;
    
    wire test_out;
    wire [7:0] debug_status;
    wire  [7:0]debug_status2;
    wire [1:0] debug_status3;    
    wire [3:0 ] TSTRB;
    reg ready;
    reg statei;
    reg [7:0]adc_input;
    reg aresetn;
    
    adc_capture_module1 test(
        adc_input,
        adcclk,
        reset,
        test_out,
        debug_status,
        debug_status2,
        debug_status3,
        clk,
        aresetn,
        tvalid,
        data,
        tstrd,
        tlast,
        ready);
        
    initial
    begin
        ready = 0;
        clk = 1;
        statei = 0;
        reset = 0;
        # 80
        
        # 160
        reset = 1;
        adc_input = 0;
        ready = 1;
        # 50000
        statei = 1;
;       # 500000
        $stop;

    end
    always 
    begin 
        #10
        clk <= ~clk;
        
        
    end
    
     always 
    begin 
        #100
        adcclk <= ~adcclk;
        adc_input = adc_input + 1;
        
    end

endmodule