From 87a018c1d36389103aff65903cd7ca9dc5110eaf Mon Sep 17 00:00:00 2001 From: 18650180552 Date: Fri, 6 Jan 2023 15:31:11 +0800 Subject: [PATCH] first init --- hdl/adc_capture_module.v | 453 +++++++++++++++++++++++++++++++++++++++ hdl/test_axis.v | 453 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 906 insertions(+) create mode 100644 hdl/adc_capture_module.v create mode 100644 hdl/test_axis.v diff --git a/hdl/adc_capture_module.v b/hdl/adc_capture_module.v new file mode 100644 index 0000000..20936b3 --- /dev/null +++ b/hdl/adc_capture_module.v @@ -0,0 +1,453 @@ +`timescale 1ns / 1ps +module adc_capture_module # +( + parameter [7:0] C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter [7:0] C_M_START_COUNT = 32, + + parameter [7:0] CAPTURE_STATUS_STOP = 8'd1, // 停止发送 + parameter [7:0] CAPTURE_STATUS_CAPTURING = 8'd0, // 发送中 + parameter [7:0] CAPTURE_STATUS_SEND_START = 8'd2, // 开始采集 + + parameter [7:0] SEND_STATUS_STOP = 8'd1, // 停止发送 + parameter [7:0] SEND_STATUS_SENDING = 8'd0, // 发送中 + parameter [7:0] SEND_STATUS_SEND_START = 8'd2, // 开始采集 + parameter [7:0] SEND_STATUS_IDLE = 8'd3, // 空闲中 + + + parameter [7:0] BUFFER_STATUS_FULL = 8'd00, // 1缓冲区满 + parameter [7:0] BUFFER_STATUS_SENDING = 8'd2, // 发送中 + parameter [7:0] BUFFER_STATUS_CAPTURING = 8'd3, // 采集中 + parameter [7:0] BUFFER_STATUS_EMPTY = 8'd4 // 缓冲区状态为空 +) +( + adc_input, + adc_clk, + reset_n, + test_out, + debug_status, + debug_status2, + debug_status3, + // Global ports + M_AXIS_ACLK, + // + M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY + ); + wire M_AXIS_ACLK; + input M_AXIS_ACLK; + + input wire M_AXIS_ARESETN; + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + wire M_AXIS_TVALID; + output M_AXIS_TVALID; + reg m_axis_tvalid; + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH - 1 : 0] M_AXIS_TDATA; + reg [63:0] package_cnt; + reg [C_M_AXIS_TDATA_WIDTH - 1 : 0] m_axis_tdata; + assign M_AXIS_TDATA = m_axis_tdata; + + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8) - 1 : 0] M_AXIS_TSTRB; + + assign M_AXIS_TSTRB = 4'b1111; + // TLAST indicates the boundary of a packet. + wire M_AXIS_TLAST; + output M_AXIS_TLAST; + reg m_axis_tlast; + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY; + + reg TestOut; + wire test_out; + wire [7:0]debug_status; + wire [7:0]debug_status2; + wire [1:0]debug_status3; + + output [7:0]debug_status; + output [7:0]debug_status2; + output [1:0]debug_status3; + + output test_out; + assign test_out = TestOut; + + wire reset_n; + input reset_n; + wire adc_clk; + input adc_clk; + wire [7:0] adc_input; + input [7:0] adc_input; + reg [7:0] store_data1 [0:135]; + reg [7:0] store_data2 [0:135]; + reg [7:0] current_send_buffer; + reg [7:0] current_capture_buffer; + reg [7:0] send_count; + reg [7:0] status_capture; // adc采集状态机 + reg [7:0] status_send = SEND_STATUS_IDLE; // axi发送状态机 + reg [7:0] status_action_send; // axi当前发送状态机 + + reg [15:0] tmp1; + reg [7:0] status_buffer1; // 缓冲区1状态状态 + reg [7:0] status_buffer2; // 缓冲区2状态状态 + reg [7:0] for_debug; + reg [7:0] for_debug2; + reg [1:0] for_debug3; + + assign M_AXIS_TVALID = m_axis_tvalid; + assign debug_status = for_debug; + assign debug_status2 = for_debug2; + assign debug_status3 = for_debug3; + assign M_AXIS_TLAST = m_axis_tlast; + + reg [8:0] cnt; + reg [2:0] state; + + reg [7:0]send_start_flag = 0; + reg first_flag_for_send = 0; + + always@(posedge adc_clk) + begin + if(reset_n == 0) + begin + cnt = 0; + store_data1[0] = 0; + TestOut = 1'b0; + status_buffer1 = BUFFER_STATUS_EMPTY; + status_buffer2 = BUFFER_STATUS_EMPTY; + package_cnt = 0; + current_capture_buffer = 1; + status_capture = CAPTURE_STATUS_STOP; + for_debug = 8'd50; + current_send_buffer = 1; + send_start_flag = 0; + end + // 采集,和发送切换的状态机 + if({status_buffer1,status_buffer2} == {BUFFER_STATUS_EMPTY,BUFFER_STATUS_EMPTY}) + begin + current_capture_buffer = 1; + status_capture = CAPTURE_STATUS_SEND_START; + for_debug = 8'd1; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_FULL,BUFFER_STATUS_EMPTY}) + begin + current_capture_buffer = 2; + status_capture = CAPTURE_STATUS_SEND_START; + current_send_buffer = 1; + if({send_start_flag, status_send} == {1'b0,SEND_STATUS_IDLE}) + begin + send_start_flag = 1; + end + for_debug = 8'd2; + status_buffer1 = BUFFER_STATUS_SENDING; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_EMPTY,BUFFER_STATUS_FULL}) + begin + current_capture_buffer = 1; + status_capture = CAPTURE_STATUS_SEND_START; + current_send_buffer = 2; + if({send_start_flag, status_send} == {1'b0,SEND_STATUS_IDLE}) + begin + send_start_flag = 1; + end + for_debug = 8'd3; + status_buffer2 = BUFFER_STATUS_SENDING; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_FULL,BUFFER_STATUS_FULL}) // 1,2 都满 按理说这种情况不应该发生 + begin + current_send_buffer = 1; + if({send_start_flag, status_send} == {1'b0,SEND_STATUS_IDLE}) + begin + send_start_flag = 1; + end + for_debug = 8'd11; + status_buffer1 = BUFFER_STATUS_SENDING; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_CAPTURING,BUFFER_STATUS_CAPTURING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + // + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_SENDING,BUFFER_STATUS_CAPTURING}) //1个发送,1个在采集 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer1 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd5; + + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_SENDING,BUFFER_STATUS_FULL}) // + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer1 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd6; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_SENDING,BUFFER_STATUS_EMPTY}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer1 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd7; + + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_EMPTY,BUFFER_STATUS_SENDING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer2 = BUFFER_STATUS_EMPTY; + + end + for_debug = 8'd8; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_CAPTURING,BUFFER_STATUS_SENDING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer2 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd9; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_FULL,BUFFER_STATUS_SENDING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer2 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd10; + end + + + // 采集状态机 + // 同一时间只有一个采集通道 + if(status_capture == CAPTURE_STATUS_STOP) + status_capture = CAPTURE_STATUS_STOP; + + if(status_capture == CAPTURE_STATUS_CAPTURING) + begin + if(current_capture_buffer == 1'd1) // 1 缓冲区 + begin + package_cnt = package_cnt + 1; + store_data1[cnt + 8] = adc_input; + store_data1[0] = package_cnt[7:0]; + store_data1[1] = package_cnt[15:8]; + store_data1[2] = package_cnt[23:16]; + store_data1[3] = package_cnt[31:24]; + store_data1[4] = package_cnt[39:32]; + store_data1[5] = package_cnt[47:40]; + store_data1[6] = package_cnt[55:48]; + store_data1[7] = package_cnt[63:56]; + + + cnt = cnt + 1; + TestOut = 0; + if(cnt == 8'd128) + begin + cnt = 8'd0; + TestOut = 1; + status_buffer1 = BUFFER_STATUS_FULL; + status_capture = CAPTURE_STATUS_STOP; + end + end + if(current_capture_buffer == 8'd2) // 2 缓冲区 + begin + package_cnt = package_cnt + 1; + store_data2[cnt + 8] = adc_input; + store_data2[0] = package_cnt[7:0]; + store_data2[1] = package_cnt[15:8]; + store_data2[2] = package_cnt[23:16]; + store_data2[3] = package_cnt[31:24]; + store_data2[4] = package_cnt[39:32]; + store_data2[5] = package_cnt[47:40]; + store_data2[6] = package_cnt[55:48]; + store_data2[7] = package_cnt[63:56]; + + cnt = cnt + 1; + TestOut = 0; + if(cnt == 8'd128) + begin + cnt = 8'd0; + TestOut = 1; + status_buffer2 = BUFFER_STATUS_FULL; + status_capture = CAPTURE_STATUS_STOP; + end + end + + end + if(status_capture == CAPTURE_STATUS_SEND_START) + begin + if(current_capture_buffer == 8'd1) + begin + store_data1[cnt + 8] = adc_input; + status_buffer1 = BUFFER_STATUS_CAPTURING; + end + if(current_capture_buffer == 8'd2) + begin + store_data2[cnt + 8] = adc_input; + status_buffer2 = BUFFER_STATUS_CAPTURING; + end + cnt = 1; + status_capture = CAPTURE_STATUS_CAPTURING; + end + end + + // 发送状态机 + always@(posedge M_AXIS_ACLK) + begin + if(reset_n == 0) + begin + status_send = SEND_STATUS_IDLE; + m_axis_tvalid = 1; + m_axis_tdata = 1; + send_count = 0; + m_axis_tlast = 0; + end + else begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_IDLE}) + begin + status_send = SEND_STATUS_SEND_START; + for_debug2 = 8'd1; + m_axis_tlast = 0; + m_axis_tvalid = 0; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_STOP}) + begin + status_send = SEND_STATUS_IDLE; + m_axis_tvalid = 0; + m_axis_tlast = 0; + for_debug2 = 8'd2; + end + else if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + m_axis_tvalid = 0; + m_axis_tlast = 0; + for_debug2 = 8'd12; + end + else if({send_start_flag,status_send} == {8'd1,SEND_STATUS_SEND_START}) // 开始发送 + begin + for_debug3 = {M_AXIS_TREADY,m_axis_tvalid}; + for_debug2 = 8'd3; + m_axis_tvalid = 1; + send_count = 0; + m_axis_tlast = 0; + if(current_send_buffer == 1) + begin + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + m_axis_tdata = { + store_data1[send_count], + store_data1[send_count + 1], + store_data1[send_count + 2], + store_data1[send_count + 3]}; + send_count = send_count + 4; + end + end + else if(current_send_buffer == 2) + begin + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + m_axis_tdata = { + store_data2[send_count], + store_data2[send_count + 1], + store_data2[send_count + 2], + store_data2[send_count + 3]}; + send_count = send_count + 4; + end + end + status_send = SEND_STATUS_SENDING; + end + else if(status_send == SEND_STATUS_SENDING) + begin + for_debug3 = {M_AXIS_TREADY,m_axis_tvalid}; + m_axis_tvalid = 1; + m_axis_tlast = 0; + + for_debug2 = 8'd4; + if(current_send_buffer == 1) + begin + for_debug2 = 8'd5; + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + m_axis_tdata = { + store_data1[send_count], + store_data1[send_count + 1], + store_data1[send_count + 2], + store_data1[send_count + 3]}; + send_count = send_count + 4; + if(send_count == 8'd136) + begin + status_send = SEND_STATUS_STOP; + send_count = 0; + m_axis_tlast = 1; + end + end + end + else if(current_send_buffer == 2) + begin + for_debug2 = 8'd10; + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + for_debug2 = 8'd6; + m_axis_tdata = { + store_data2[send_count], + store_data2[send_count + 1], + store_data2[send_count + 2], + store_data2[send_count + 3]}; + send_count = send_count + 4; + if(send_count == 8'd136) + begin + status_send = SEND_STATUS_STOP; + send_count = 0; + m_axis_tlast = 1; + end + end + end + end + end +end +endmodule \ No newline at end of file diff --git a/hdl/test_axis.v b/hdl/test_axis.v new file mode 100644 index 0000000..02ae5cc --- /dev/null +++ b/hdl/test_axis.v @@ -0,0 +1,453 @@ +`timescale 1ns / 1ps +module adc_capture_module1 # +( + parameter [7:0] C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter [7:0] C_M_START_COUNT = 32, + + parameter [7:0] CAPTURE_STATUS_STOP = 8'd1, // 停止发送 + parameter [7:0] CAPTURE_STATUS_CAPTURING = 8'd0, // 发送中 + parameter [7:0] CAPTURE_STATUS_SEND_START = 8'd2, // 开始采集 + + parameter [7:0] SEND_STATUS_STOP = 8'd1, // 停止发送 + parameter [7:0] SEND_STATUS_SENDING = 8'd0, // 发送中 + parameter [7:0] SEND_STATUS_SEND_START = 8'd2, // 开始采集 + parameter [7:0] SEND_STATUS_IDLE = 8'd3, // 空闲中 + + + parameter [7:0] BUFFER_STATUS_FULL = 8'd00, // 1缓冲区满 + parameter [7:0] BUFFER_STATUS_SENDING = 8'd2, // 发送中 + parameter [7:0] BUFFER_STATUS_CAPTURING = 8'd3, // 采集中 + parameter [7:0] BUFFER_STATUS_EMPTY = 8'd4 // 缓冲区状态为空 +) +( + adc_input, + adc_clk, + reset_n, + test_out, + debug_status, + debug_status2, + debug_status3, + // Global ports + M_AXIS_ACLK, + // + M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY + ); + wire M_AXIS_ACLK; + input M_AXIS_ACLK; + + input wire M_AXIS_ARESETN; + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + wire M_AXIS_TVALID; + output M_AXIS_TVALID; + reg m_axis_tvalid; + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH - 1 : 0] M_AXIS_TDATA; + reg [63:0] package_cnt; + reg [C_M_AXIS_TDATA_WIDTH - 1 : 0] m_axis_tdata; + assign M_AXIS_TDATA = m_axis_tdata; + + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8) - 1 : 0] M_AXIS_TSTRB; + + assign M_AXIS_TSTRB = 4'b1111; + // TLAST indicates the boundary of a packet. + wire M_AXIS_TLAST; + output M_AXIS_TLAST; + reg m_axis_tlast; + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY; + + reg TestOut; + wire test_out; + wire [7:0]debug_status; + wire [7:0]debug_status2; + wire [1:0]debug_status3; + + output [7:0]debug_status; + output [7:0]debug_status2; + output [1:0]debug_status3; + + output test_out; + assign test_out = TestOut; + + wire reset_n; + input reset_n; + wire adc_clk; + input adc_clk; + wire [7:0] adc_input; + input [7:0] adc_input; + reg [7:0] store_data1 [0:135]; + reg [7:0] store_data2 [0:135]; + reg [7:0] current_send_buffer; + reg [7:0] current_capture_buffer; + reg [7:0] send_count; + reg [7:0] status_capture; // adc采集状态机 + reg [7:0] status_send = SEND_STATUS_IDLE; // axi发送状态机 + reg [7:0] status_action_send; // axi当前发送状态机 + + reg [15:0] tmp1; + reg [7:0] status_buffer1; // 缓冲区1状态状态 + reg [7:0] status_buffer2; // 缓冲区2状态状态 + reg [7:0] for_debug; + reg [7:0] for_debug2; + reg [1:0] for_debug3; + + assign M_AXIS_TVALID = m_axis_tvalid; + assign debug_status = for_debug; + assign debug_status2 = for_debug2; + assign debug_status3 = for_debug3; + assign M_AXIS_TLAST = m_axis_tlast; + + reg [8:0] cnt; + reg [2:0] state; + + reg [7:0]send_start_flag = 0; + reg first_flag_for_send = 0; + + always@(posedge adc_clk) + begin + if(reset_n == 0) + begin + cnt = 0; + store_data1[0] = 0; + TestOut = 1'b0; + status_buffer1 = BUFFER_STATUS_EMPTY; + status_buffer2 = BUFFER_STATUS_EMPTY; + package_cnt = 0; + current_capture_buffer = 1; + status_capture = CAPTURE_STATUS_STOP; + for_debug = 8'd50; + current_send_buffer = 1; + send_start_flag = 0; + end + // 采集,和发送切换的状态机 + if({status_buffer1,status_buffer2} == {BUFFER_STATUS_EMPTY,BUFFER_STATUS_EMPTY}) + begin + current_capture_buffer = 1; + status_capture = CAPTURE_STATUS_SEND_START; + for_debug = 8'd1; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_FULL,BUFFER_STATUS_EMPTY}) + begin + current_capture_buffer = 2; + status_capture = CAPTURE_STATUS_SEND_START; + current_send_buffer = 1; + if({send_start_flag, status_send} == {1'b0,SEND_STATUS_IDLE}) + begin + send_start_flag = 1; + end + for_debug = 8'd2; + status_buffer1 = BUFFER_STATUS_SENDING; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_EMPTY,BUFFER_STATUS_FULL}) + begin + current_capture_buffer = 1; + status_capture = CAPTURE_STATUS_SEND_START; + current_send_buffer = 2; + if({send_start_flag, status_send} == {1'b0,SEND_STATUS_IDLE}) + begin + send_start_flag = 1; + end + for_debug = 8'd3; + status_buffer2 = BUFFER_STATUS_SENDING; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_FULL,BUFFER_STATUS_FULL}) // 1,2 都满 按理说这种情况不应该发生 + begin + current_send_buffer = 1; + if({send_start_flag, status_send} == {1'b0,SEND_STATUS_IDLE}) + begin + send_start_flag = 1; + end + for_debug = 8'd11; + status_buffer1 = BUFFER_STATUS_SENDING; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_CAPTURING,BUFFER_STATUS_CAPTURING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + // + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_SENDING,BUFFER_STATUS_CAPTURING}) //1个发送,1个在采集 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer1 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd5; + + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_SENDING,BUFFER_STATUS_FULL}) // + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer1 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd6; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_SENDING,BUFFER_STATUS_EMPTY}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer1 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd7; + + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_EMPTY,BUFFER_STATUS_SENDING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer2 = BUFFER_STATUS_EMPTY; + + end + for_debug = 8'd8; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_CAPTURING,BUFFER_STATUS_SENDING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer2 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd9; + end + else if({status_buffer1,status_buffer2} == {BUFFER_STATUS_FULL,BUFFER_STATUS_SENDING}) // 1,2 都在采集状态,不可能出现这种情况 + begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + send_start_flag = 8'd2; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_IDLE}) + begin + send_start_flag = 8'd0; + status_buffer2 = BUFFER_STATUS_EMPTY; + end + for_debug = 8'd10; + end + + + // 采集状态机 + // 同一时间只有一个采集通道 + if(status_capture == CAPTURE_STATUS_STOP) + status_capture = CAPTURE_STATUS_STOP; + + if(status_capture == CAPTURE_STATUS_CAPTURING) + begin + if(current_capture_buffer == 1'd1) // 1 缓冲区 + begin + package_cnt = package_cnt + 1; + store_data1[cnt + 8] = adc_input; + store_data1[0] = package_cnt[7:0]; + store_data1[1] = package_cnt[15:8]; + store_data1[2] = package_cnt[23:16]; + store_data1[3] = package_cnt[31:24]; + store_data1[4] = package_cnt[39:32]; + store_data1[5] = package_cnt[47:40]; + store_data1[6] = package_cnt[55:48]; + store_data1[7] = package_cnt[63:56]; + + + cnt = cnt + 1; + TestOut = 0; + if(cnt == 8'd128) + begin + cnt = 8'd0; + TestOut = 1; + status_buffer1 = BUFFER_STATUS_FULL; + status_capture = CAPTURE_STATUS_STOP; + end + end + if(current_capture_buffer == 8'd2) // 2 缓冲区 + begin + package_cnt = package_cnt + 1; + store_data2[cnt + 8] = adc_input; + store_data2[0] = package_cnt[7:0]; + store_data2[1] = package_cnt[15:8]; + store_data2[2] = package_cnt[23:16]; + store_data2[3] = package_cnt[31:24]; + store_data2[4] = package_cnt[39:32]; + store_data2[5] = package_cnt[47:40]; + store_data2[6] = package_cnt[55:48]; + store_data2[7] = package_cnt[63:56]; + + cnt = cnt + 1; + TestOut = 0; + if(cnt == 8'd128) + begin + cnt = 8'd0; + TestOut = 1; + status_buffer2 = BUFFER_STATUS_FULL; + status_capture = CAPTURE_STATUS_STOP; + end + end + + end + if(status_capture == CAPTURE_STATUS_SEND_START) + begin + if(current_capture_buffer == 8'd1) + begin + store_data1[cnt + 8] = adc_input; + status_buffer1 = BUFFER_STATUS_CAPTURING; + end + if(current_capture_buffer == 8'd2) + begin + store_data2[cnt + 8] = adc_input; + status_buffer2 = BUFFER_STATUS_CAPTURING; + end + cnt = 1; + status_capture = CAPTURE_STATUS_CAPTURING; + end + end + + // 发送状态机 + always@(posedge M_AXIS_ACLK) + begin + if(reset_n == 0) + begin + status_send = SEND_STATUS_IDLE; + m_axis_tvalid = 1; + m_axis_tdata = 1; + send_count = 0; + m_axis_tlast = 0; + end + else begin + if({send_start_flag,status_send} == {8'd1,SEND_STATUS_IDLE}) + begin + status_send = SEND_STATUS_SEND_START; + for_debug2 = 8'd1; + m_axis_tlast = 0; + m_axis_tvalid = 0; + + end + else if({send_start_flag,status_send} == {8'd2,SEND_STATUS_STOP}) + begin + status_send = SEND_STATUS_IDLE; + m_axis_tvalid = 0; + m_axis_tlast = 0; + for_debug2 = 8'd2; + end + else if({send_start_flag,status_send} == {8'd1,SEND_STATUS_STOP}) + begin + m_axis_tvalid = 0; + m_axis_tlast = 0; + for_debug2 = 8'd12; + end + else if({send_start_flag,status_send} == {8'd1,SEND_STATUS_SEND_START}) // 开始发送 + begin + for_debug3 = {M_AXIS_TREADY,m_axis_tvalid}; + for_debug2 = 8'd3; + m_axis_tvalid = 1; + send_count = 0; + m_axis_tlast = 0; + if(current_send_buffer == 1) + begin + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + m_axis_tdata = { + store_data1[send_count], + store_data1[send_count + 1], + store_data1[send_count + 2], + store_data1[send_count + 3]}; + send_count = send_count + 4; + end + end + else if(current_send_buffer == 2) + begin + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + m_axis_tdata = { + store_data2[send_count], + store_data2[send_count + 1], + store_data2[send_count + 2], + store_data2[send_count + 3]}; + send_count = send_count + 4; + end + end + status_send = SEND_STATUS_SENDING; + end + else if(status_send == SEND_STATUS_SENDING) + begin + for_debug3 = {M_AXIS_TREADY,m_axis_tvalid}; + m_axis_tvalid = 1; + m_axis_tlast = 0; + + for_debug2 = 8'd4; + if(current_send_buffer == 1) + begin + for_debug2 = 8'd5; + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + m_axis_tdata = { + store_data1[send_count], + store_data1[send_count + 1], + store_data1[send_count + 2], + store_data1[send_count + 3]}; + send_count = send_count + 4; + if(send_count == 8'd136) + begin + status_send = SEND_STATUS_STOP; + send_count = 0; + m_axis_tlast = 1; + end + end + end + else if(current_send_buffer == 2) + begin + for_debug2 = 8'd10; + if({M_AXIS_TREADY,m_axis_tvalid} == {1'b1,1'b1}) + begin + for_debug2 = 8'd6; + m_axis_tdata = { + store_data2[send_count], + store_data2[send_count + 1], + store_data2[send_count + 2], + store_data2[send_count + 3]}; + send_count = send_count + 4; + if(send_count == 8'd136) + begin + status_send = SEND_STATUS_STOP; + send_count = 0; + m_axis_tlast = 1; + end + end + end + end + end +end +endmodule \ No newline at end of file