77 lines
1.2 KiB
Coq
77 lines
1.2 KiB
Coq
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`timescale 1ns / 1ps
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module simu(
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);
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reg clk = 0;
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reg adcclk = 0;
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reg reset = 1;
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
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wire [31:0]data;
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wire tvalid;
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wire [3:0]tstrd;
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wire tlast;
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wire test_out;
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wire [7:0] debug_status;
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wire [7:0]debug_status2;
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wire [1:0] debug_status3;
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wire [3:0 ] TSTRB;
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reg ready;
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reg statei;
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reg [7:0]adc_input;
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reg aresetn;
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adc_capture_module1 test(
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adc_input,
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adcclk,
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reset,
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test_out,
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debug_status,
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debug_status2,
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debug_status3,
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clk,
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aresetn,
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tvalid,
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data,
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tstrd,
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tlast,
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ready);
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initial
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begin
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ready = 0;
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clk = 1;
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statei = 0;
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reset = 0;
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# 80
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# 160
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reset = 1;
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adc_input = 0;
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ready = 1;
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# 50000
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statei = 1;
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; # 500000
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$stop;
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end
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always
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begin
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#10
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clk <= ~clk;
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end
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always
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begin
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#100
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adcclk <= ~adcclk;
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adc_input = adc_input + 1;
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end
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endmodule
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