1671 lines
305 KiB
Plaintext
1671 lines
305 KiB
Plaintext
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*** Running vivado
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with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
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****** Vivado v2018.3 (64-bit)
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**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source design_1_wrapper.tcl -notrace
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'l:/PersonalProjects/Xilinx/ip_repo/PL_IOcontrol/PL_IOcontrol_1.0'.
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WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer4/ip_repo/direct_fft_1.0'; Can't find the specified path.
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If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'l:/PersonalProjects/Xilinx/SpecialSources'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip'.
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WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
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Current IP cache path is L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.cache/ip
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add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 372.098 ; gain = 106.129
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Command: link_design -top design_1_wrapper -part xc7z035ffg676-2
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_adc_read_0_0/design_1_adc_read_0_0.dcp' for cell 'design_1_i/adc_read_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0.dcp' for cell 'design_1_i/axi_dma_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_dynclk_0_2/design_1_axi_dynclk_0_2.dcp' for cell 'design_1_i/axi_dynclk_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.dcp' for cell 'design_1_i/axi_gpio_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/design_1_axi_gpio_1_0.dcp' for cell 'design_1_i/axi_gpio_1'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_2/design_1_axi_smc_2.dcp' for cell 'design_1_i/axi_smc'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc1_0/design_1_axi_smc1_0.dcp' for cell 'design_1_i/axi_smc1'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_2/design_1_axi_vdma_0_2.dcp' for cell 'design_1_i/axi_vdma_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp' for cell 'design_1_i/clk_wiz_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_direct_fft_0_0/design_1_direct_fft_0_0.dcp' for cell 'design_1_i/direct_fft_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_key_ec11_0_1/design_1_key_ec11_0_1.dcp' for cell 'design_1_i/key_ec11_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rgb2dvi_0_2/design_1_rgb2dvi_0_2.dcp' for cell 'design_1_i/rgb2dvi_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_2/design_1_rst_ps7_0_100M_2.dcp' for cell 'design_1_i/rst_ps7_0_100M'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_142M_2/design_1_rst_ps7_0_142M_2.dcp' for cell 'design_1_i/rst_ps7_0_142M'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_250M_0/design_1_rst_ps7_0_250M_0.dcp' for cell 'design_1_i/rst_ps7_0_250M'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.dcp' for cell 'design_1_i/util_vector_logic_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_axi4s_vid_out_0_2/design_1_v_axi4s_vid_out_0_2.dcp' for cell 'design_1_i/v_axi4s_vid_out_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_tc_0_2/design_1_v_tc_0_2.dcp' for cell 'design_1_i/v_tc_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_window_0_0/design_1_window_0_0.dcp' for cell 'design_1_i/window_0'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_xbar_2/design_1_xbar_2.dcp' for cell 'design_1_i/ps7_0_axi_periph/xbar'
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INFO: [Project 1-454] Reading design checkpoint 'l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.dcp' for cell 'design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc'
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INFO: [Netlist 29-17] Analyzing 2268 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7z035ffg676-2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'design_1_i/direct_fft_0/inst/fifo_f1/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1.xdc] for cell 'design_1_i/direct_fft_0/inst/fifo_f1/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0.xdc] for cell 'design_1_i/axi_dma_0/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0.xdc] for cell 'design_1_i/axi_dma_0/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc1_0/bd_0/ip/ip_1/bd_68a3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc1/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc1_0/bd_0/ip/ip_1/bd_68a3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc1/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc1_0/bd_0/ip/ip_1/bd_68a3_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc1/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc1_0/bd_0/ip/ip_1/bd_68a3_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc1/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:57]
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get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1670.508 ; gain = 647.391
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_250M_0/design_1_rst_ps7_0_250M_0_board.xdc] for cell 'design_1_i/rst_ps7_0_250M/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_250M_0/design_1_rst_ps7_0_250M_0_board.xdc] for cell 'design_1_i/rst_ps7_0_250M/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_250M_0/design_1_rst_ps7_0_250M_0.xdc] for cell 'design_1_i/rst_ps7_0_250M/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_250M_0/design_1_rst_ps7_0_250M_0.xdc] for cell 'design_1_i/rst_ps7_0_250M/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_2/bd_0/ip/ip_1/bd_6e42_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_2/bd_0/ip/ip_1/bd_6e42_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_2/bd_0/ip/ip_1/bd_6e42_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_2/bd_0/ip/ip_1/bd_6e42_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_2/design_1_axi_vdma_0_2.xdc] for cell 'design_1_i/axi_vdma_0/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_2/design_1_axi_vdma_0_2.xdc] for cell 'design_1_i/axi_vdma_0/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rgb2dvi_0_2/src/rgb2dvi.xdc] for cell 'design_1_i/rgb2dvi_0/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rgb2dvi_0_2/src/rgb2dvi.xdc] for cell 'design_1_i/rgb2dvi_0/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_2/design_1_rst_ps7_0_100M_2_board.xdc] for cell 'design_1_i/rst_ps7_0_100M/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_2/design_1_rst_ps7_0_100M_2_board.xdc] for cell 'design_1_i/rst_ps7_0_100M/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_2/design_1_rst_ps7_0_100M_2.xdc] for cell 'design_1_i/rst_ps7_0_100M/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_2/design_1_rst_ps7_0_100M_2.xdc] for cell 'design_1_i/rst_ps7_0_100M/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_142M_2/design_1_rst_ps7_0_142M_2_board.xdc] for cell 'design_1_i/rst_ps7_0_142M/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_142M_2/design_1_rst_ps7_0_142M_2_board.xdc] for cell 'design_1_i/rst_ps7_0_142M/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_142M_2/design_1_rst_ps7_0_142M_2.xdc] for cell 'design_1_i/rst_ps7_0_142M/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_142M_2/design_1_rst_ps7_0_142M_2.xdc] for cell 'design_1_i/rst_ps7_0_142M/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'design_1_i/axi_gpio_0/U0'
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Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'design_1_i/axi_gpio_0/U0'
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Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'design_1_i/axi_gpio_0/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'design_1_i/axi_gpio_0/U0'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/design_1_axi_gpio_1_0_board.xdc] for cell 'design_1_i/axi_gpio_1/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/design_1_axi_gpio_1_0_board.xdc] for cell 'design_1_i/axi_gpio_1/U0'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/design_1_axi_gpio_1_0.xdc] for cell 'design_1_i/axi_gpio_1/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/design_1_axi_gpio_1_0.xdc] for cell 'design_1_i/axi_gpio_1/U0'
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|
Parsing XDC File [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc]
|
|
WARNING: [Vivado 12-584] No ports matched 'IIC_0_0_scl_io'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:3]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:3]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'IIC_0_0_sda_io'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:4]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:4]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'IIC_0_0_scl_io'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:7]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:7]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'IIC_0_0_sda_io'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:8]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:8]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:24]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:24]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:25]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:25]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:26]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:26]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:27]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:27]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:28]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:28]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:31]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:31]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:32]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:32]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tvalid'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:34]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:34]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'valid_0'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:36]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:36]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'valid_0'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:37]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:37]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[15]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:39]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:39]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[14]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:40]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:40]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[13]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:41]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:41]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[12]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:42]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:42]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[11]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:43]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:43]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[10]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:44]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:44]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[9]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:45]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:45]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[8]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:46]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:46]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:47]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:47]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:48]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:48]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:49]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:49]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:50]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:50]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:51]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:51]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:52]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:52]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:53]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:53]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:54]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:54]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:55]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:55]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[8]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:56]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:56]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[9]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:57]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:57]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[10]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:58]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:58]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[11]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:59]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:59]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[12]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:60]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:60]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[13]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:61]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:61]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[14]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:62]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:62]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'GPIO_0_0_tri_io[15]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:63]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:63]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 's_axis_s2mm_tready_0'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:65]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:65]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 's_axis_s2mm_tready_0'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:66]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:66]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[9]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:115]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:115]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[8]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:116]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:116]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:117]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:117]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:118]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:118]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:119]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:119]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:120]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:120]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:121]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:121]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:122]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:122]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:123]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:123]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'dma_cnt[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:124]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:124]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:125]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:125]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:126]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:126]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:127]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:127]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:128]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:128]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:129]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:129]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:130]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:130]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:131]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:131]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_a[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:132]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:132]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:133]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:133]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:134]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:134]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:135]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:135]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:136]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:136]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:137]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:137]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:138]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:138]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:139]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:139]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tkeep[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:140]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:140]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:141]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:141]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:142]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:142]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:143]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:143]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:144]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:144]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:145]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:145]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:146]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:146]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:147]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:147]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'port_b[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:148]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:148]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'pll_rst'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:149]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:149]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'sel_clk'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:150]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:150]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'rst'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:151]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:151]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'pwdn'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:152]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:152]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'power_en'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:153]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:153]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'locked0'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:154]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:154]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tlast'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:155]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:155]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'm_axis_data_tready'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:156]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:156]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'pll_en'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:157]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:157]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[10]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:158]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:158]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[9]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:159]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:159]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[8]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:160]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:160]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[7]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:161]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:161]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[6]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:162]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:162]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[5]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:163]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:163]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[4]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:164]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:164]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[3]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:165]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:165]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[2]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:166]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:166]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[1]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:167]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:167]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_index[0]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:168]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:168]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'sys_clk'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:169]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:169]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_abs[26]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:170]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:170]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_abs[25]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:171]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:171]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_abs[24]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:172]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:172]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
WARNING: [Vivado 12-584] No ports matched 'fft_abs[23]'. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:173]
|
|
INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:173]
|
|
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:173]
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|
INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc:173]
|
|
Finished Parsing XDC File [L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/constrs_1/hdmi7035.xdc]
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_clocks.xdc] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0_clocks.xdc] for cell 'design_1_i/axi_dma_0/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/design_1_axi_dma_0_0_clocks.xdc] for cell 'design_1_i/axi_dma_0/U0'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_2/design_1_axi_vdma_0_2_clocks.xdc] for cell 'design_1_i/axi_vdma_0/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_2/design_1_axi_vdma_0_2_clocks.xdc] for cell 'design_1_i/axi_vdma_0/U0'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rgb2dvi_0_2/src/rgb2dvi_clocks.xdc] for cell 'design_1_i/rgb2dvi_0/U0'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_rgb2dvi_0_2/src/rgb2dvi_clocks.xdc] for cell 'design_1_i/rgb2dvi_0/U0'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_axi4s_vid_out_0_2/design_1_v_axi4s_vid_out_0_2_clocks.xdc] for cell 'design_1_i/v_axi4s_vid_out_0/inst'
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_axi4s_vid_out_0_2/design_1_v_axi4s_vid_out_0_2_clocks.xdc] for cell 'design_1_i/v_axi4s_vid_out_0/inst'
|
|
Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_tc_0_2/design_1_v_tc_0_2_clocks.xdc] for cell 'design_1_i/v_tc_0/U0'
|
|
INFO: [Timing 38-2] Deriving generated clocks [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_tc_0_2/design_1_v_tc_0_2_clocks.xdc:2]
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O. [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_tc_0_2/design_1_v_tc_0_2_clocks.xdc:2]
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
Finished Parsing XDC File [l:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.srcs/sources_1/bd/design_1/ip/design_1_v_tc_0_2/design_1_v_tc_0_2_clocks.xdc] for cell 'design_1_i/v_tc_0/U0'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/CDC_SINGLE_LOCKED_INST/xpm_cdc_single_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/CDC_SINGLE_LOCKED_INST/xpm_cdc_single_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/CDC_SINGLE_REMAP_UNDERFLOW_INST/xpm_cdc_single_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/CDC_SINGLE_REMAP_UNDERFLOW_INST/xpm_cdc_single_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
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Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
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|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
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|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst'
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|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst'
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|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst'
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|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst'
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Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST'
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|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc1/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc1/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc1/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc1/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
Finished Sourcing Tcl File [T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1679.453 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 315 instances were transformed.
|
|
CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 212 instances
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 93 instances
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 10 instances
|
|
|
|
40 Infos, 102 Warnings, 101 Critical Warnings and 0 Errors encountered.
|
|
link_design completed successfully
|
|
link_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1679.453 ; gain = 1307.355
|
|
Command: opt_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
|
Running DRC as a precondition to command opt_design
|
|
|
|
Starting DRC Task
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Project 1-461] DRC finished with 0 Errors
|
|
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.661 . Memory (MB): peak = 1679.453 ; gain = 0.000
|
|
|
|
Starting Cache Timing Information Task
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Ending Cache Timing Information Task | Checksum: 298af6450
|
|
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1679.453 ; gain = 0.000
|
|
|
|
Starting Logic Optimization Task
|
|
|
|
Phase 1 Generate And Synthesize Debug Cores
|
|
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
|
|
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
|
|
INFO: [Chipscope 16-220] Re-using generated and synthesized IP, "xilinx.com:ip:xsdbm:3.0", from Vivado IP cache entry "4aa5b9bb4c9ef7b5".
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1786.156 ; gain = 0.000
|
|
Phase 1 Generate And Synthesize Debug Cores | Checksum: 1dae142cb
|
|
|
|
Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1786.156 ; gain = 23.336
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
|
|
Phase 2 Retarget
|
|
INFO: [Opt 31-138] Pushed 76 inverter(s) to 146 load pin(s).
|
|
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
|
Phase 2 Retarget | Checksum: 1e305f475
|
|
|
|
Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
INFO: [Opt 31-389] Phase Retarget created 623 cells and removed 992 cells
|
|
INFO: [Opt 31-1021] In phase Retarget, 273 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 3 Constant propagation
|
|
INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s).
|
|
Phase 3 Constant propagation | Checksum: 1a87eaec8
|
|
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
INFO: [Opt 31-389] Phase Constant propagation created 103 cells and removed 1239 cells
|
|
INFO: [Opt 31-1021] In phase Constant propagation, 586 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 4 Sweep
|
|
Phase 4 Sweep | Checksum: 1ac9c6858
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
INFO: [Opt 31-389] Phase Sweep created 1 cells and removed 2630 cells
|
|
INFO: [Opt 31-1021] In phase Sweep, 1363 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 5 BUFG optimization
|
|
INFO: [Opt 31-194] Inserted BUFG design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_0_BUFG_inst to drive 0 load(s) on clock net design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_0_BUFG
|
|
INFO: [Opt 31-194] Inserted BUFG design_1_i/clk_wiz_0/inst/clk_out2_design_1_clk_wiz_0_0_BUFG_inst to drive 0 load(s) on clock net design_1_i/clk_wiz_0/inst/clk_out2_design_1_clk_wiz_0_0_BUFG
|
|
INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets
|
|
Phase 5 BUFG optimization | Checksum: 1ea3437f0
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
|
|
|
Phase 6 Shift Register Optimization
|
|
Phase 6 Shift Register Optimization | Checksum: 18a637905
|
|
|
|
Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
INFO: [Opt 31-389] Phase Shift Register Optimization created 6 cells and removed 15 cells
|
|
|
|
Phase 7 Post Processing Netlist
|
|
Phase 7 Post Processing Netlist | Checksum: 1be2ef34b
|
|
|
|
Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
|
INFO: [Opt 31-1021] In phase Post Processing Netlist, 87 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
Opt_design Change Summary
|
|
=========================
|
|
|
|
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Retarget | 623 | 992 | 273 |
|
|
| Constant propagation | 103 | 1239 | 586 |
|
|
| Sweep | 1 | 2630 | 1363 |
|
|
| BUFG optimization | 0 | 0 | 0 |
|
|
| Shift Register Optimization | 6 | 15 | 0 |
|
|
| Post Processing Netlist | 0 | 0 | 87 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
Starting Connectivity Check Task
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1787.152 ; gain = 0.000
|
|
Ending Logic Optimization Task | Checksum: 1526e9687
|
|
|
|
Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1787.152 ; gain = 24.332
|
|
|
|
Starting Power Optimization Task
|
|
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.311 | TNS=-500.430 |
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
Running Vector-less Activity Propagation...
|
|
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
|
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
|
|
|
|
Starting PowerOpt Patch Enables Task
|
|
INFO: [Pwropt 34-162] WRITE_MODE attribute of 95 BRAM(s) out of a total of 241 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
|
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
|
Number of BRAM Ports augmented: 201 newly gated: 0 Total Ports: 482
|
|
Ending PowerOpt Patch Enables Task | Checksum: 1d3306ba3
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.831 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Ending Power Optimization Task | Checksum: 1d3306ba3
|
|
|
|
Time (s): cpu = 00:00:33 ; elapsed = 00:00:20 . Memory (MB): peak = 2928.855 ; gain = 1141.703
|
|
|
|
Starting Final Cleanup Task
|
|
|
|
Starting Logic Optimization Task
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
Ending Logic Optimization Task | Checksum: 16feef533
|
|
|
|
Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Ending Final Cleanup Task | Checksum: 16feef533
|
|
|
|
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Starting Netlist Obfuscation Task
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Ending Netlist Obfuscation Task | Checksum: 16feef533
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
76 Infos, 102 Warnings, 105 Critical Warnings and 0 Errors encountered.
|
|
opt_design completed successfully
|
|
opt_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:51 . Memory (MB): peak = 2928.855 ; gain = 1249.402
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing placer database...
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Common 17-1381] The checkpoint 'L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
|
|
Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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INFO: [Common 17-14] Message 'Designutils 20-3303' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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INFO: [Coretcl 2-168] The results of DRC are in file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.runs/impl_1/design_1_wrapper_drc_opted.rpt.
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report_drc completed successfully
|
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INFO: [Chipscope 16-240] Debug cores have already been implemented
|
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Command: place_design
|
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
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INFO: [DRC 23-27] Running DRC with 2 threads
|
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
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Running DRC as a precondition to command place_design
|
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INFO: [DRC 23-27] Running DRC with 2 threads
|
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/interrupt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/left_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/right_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[11] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[9]) which is driven by a register (design_1_i/window_0/inst/addra_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[12] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[10]) which is driven by a register (design_1_i/window_0/inst/addra_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[13] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[11]) which is driven by a register (design_1_i/window_0/inst/addra_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[14] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[12]) which is driven by a register (design_1_i/window_0/inst/addra_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ENARDEN (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/adc_read_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ENBWREN (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0[0]) which is driven by a register (design_1_i/adc_read_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/WEA[0] (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/adc_read_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/WEA[1] (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/adc_read_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/interrupt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/left_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/right_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[10] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[9]) which is driven by a register (design_1_i/window_0/inst/addra_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[11] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[10]) which is driven by a register (design_1_i/window_0/inst/addra_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[12] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[11]) which is driven by a register (design_1_i/window_0/inst/addra_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[13] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[12]) which is driven by a register (design_1_i/window_0/inst/addra_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[2] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[1]) which is driven by a register (design_1_i/window_0/inst/addra_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[3] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[2]) which is driven by a register (design_1_i/window_0/inst/addra_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[4] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[3]) which is driven by a register (design_1_i/window_0/inst/addra_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[5] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[4]) which is driven by a register (design_1_i/window_0/inst/addra_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[6] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[5]) which is driven by a register (design_1_i/window_0/inst/addra_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[7] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[6]) which is driven by a register (design_1_i/window_0/inst/addra_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[8] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[7]) which is driven by a register (design_1_i/window_0/inst/addra_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[9] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[8]) which is driven by a register (design_1_i/window_0/inst/addra_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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INFO: [DRC REQP-1725] DSP_Abus_sign_bit_alert: design_1_i/direct_fft_0/inst/floating_add_abs1/U0/i_synth/ADDSUB_OP.ADDSUB/SPEED_OP.DSP.OP/DSP48E1_BODY.ALIGN_ADD/DSP2/DSP: When using the PreAdder and USE_DPORT is TRUE, the A operand should be restricted to 24 bit two's complement (and sign extended) to avoid over/underflow in the pre-add stage.
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings, 1 Advisories
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2928.855 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15e80b450
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2928.855 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2928.855 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1200376e6
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Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2928.855 ; gain = 0.000
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Phase 1.3 Build Placer Netlist Model
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CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
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Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
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Phase 1.3 Build Placer Netlist Model | Checksum: 16e9d91b5
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Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 1.4 Constrain Clocks/Macros
|
|
Phase 1.4 Constrain Clocks/Macros | Checksum: 16e9d91b5
|
|
|
|
Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 1 Placer Initialization | Checksum: 16e9d91b5
|
|
|
|
Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 2 Global Placement
|
|
|
|
Phase 2.1 Floorplanning
|
|
Phase 2.1 Floorplanning | Checksum: 1bbf060cc
|
|
|
|
Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 2.2 Physical Synthesis In Placer
|
|
INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization.
|
|
INFO: [Physopt 32-81] Processed net design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/axi_wrapper/ce_w2c. Replicated 82 times.
|
|
INFO: [Physopt 32-232] Optimized 1 net. Created 82 new instances.
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 82 new cells, deleted 0 existing cell and moved 0 existing cell
|
|
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
|
|
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-949] No candidate nets found for HD net replication
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Summary of Physical Synthesis Optimizations
|
|
============================================
|
|
|
|
|
|
----------------------------------------------------------------------------------------------------------------------------------------
|
|
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|
----------------------------------------------------------------------------------------------------------------------------------------
|
|
| Very High Fanout | 82 | 0 | 1 | 0 | 1 | 00:00:08 |
|
|
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Total | 82 | 0 | 1 | 0 | 5 | 00:00:08 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Phase 2.2 Physical Synthesis In Placer | Checksum: 1a827eea4
|
|
|
|
Time (s): cpu = 00:00:59 ; elapsed = 00:00:44 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 2 Global Placement | Checksum: 1b5991778
|
|
|
|
Time (s): cpu = 00:01:00 ; elapsed = 00:00:45 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3 Detail Placement
|
|
|
|
Phase 3.1 Commit Multi Column Macros
|
|
Phase 3.1 Commit Multi Column Macros | Checksum: 1b5991778
|
|
|
|
Time (s): cpu = 00:01:00 ; elapsed = 00:00:46 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.2 Commit Most Macros & LUTRAMs
|
|
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 19747c091
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:49 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.3 Area Swap Optimization
|
|
Phase 3.3 Area Swap Optimization | Checksum: ef8c09a0
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:50 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.4 Pipeline Register Optimization
|
|
Phase 3.4 Pipeline Register Optimization | Checksum: 142f96470
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:50 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.5 Fast Optimization
|
|
Phase 3.5 Fast Optimization | Checksum: aff11d60
|
|
|
|
Time (s): cpu = 00:01:10 ; elapsed = 00:00:52 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.6 Small Shape Detail Placement
|
|
Phase 3.6 Small Shape Detail Placement | Checksum: bc6e3a36
|
|
|
|
Time (s): cpu = 00:01:15 ; elapsed = 00:00:57 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.7 Re-assign LUT pins
|
|
Phase 3.7 Re-assign LUT pins | Checksum: 14172ac81
|
|
|
|
Time (s): cpu = 00:01:16 ; elapsed = 00:00:58 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.8 Pipeline Register Optimization
|
|
Phase 3.8 Pipeline Register Optimization | Checksum: 166906dce
|
|
|
|
Time (s): cpu = 00:01:16 ; elapsed = 00:00:58 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3.9 Fast Optimization
|
|
Phase 3.9 Fast Optimization | Checksum: 1860bdd4e
|
|
|
|
Time (s): cpu = 00:01:20 ; elapsed = 00:01:01 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 3 Detail Placement | Checksum: 1860bdd4e
|
|
|
|
Time (s): cpu = 00:01:20 ; elapsed = 00:01:01 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 4 Post Placement Optimization and Clean-Up
|
|
|
|
Phase 4.1 Post Commit Optimization
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
|
|
Phase 4.1.1 Post Placement Optimization
|
|
Post Placement Optimization Initialization | Checksum: 1bb013acc
|
|
|
|
Phase 4.1.1.1 BUFG Insertion
|
|
INFO: [Place 46-33] Processed net design_1_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.irq_i_1_n_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-46] BUFG insertion identified 1 candidate nets, 0 success, 0 bufg driver replicated, 1 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
|
|
Phase 4.1.1.1 BUFG Insertion | Checksum: 1bb013acc
|
|
|
|
Time (s): cpu = 00:01:28 ; elapsed = 00:01:07 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.507. For the most accurate timing information please run report_timing.
|
|
Phase 4.1.1 Post Placement Optimization | Checksum: 82956856
|
|
|
|
Time (s): cpu = 00:01:40 ; elapsed = 00:01:16 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 4.1 Post Commit Optimization | Checksum: 82956856
|
|
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:17 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 4.2 Post Placement Cleanup
|
|
Phase 4.2 Post Placement Cleanup | Checksum: 82956856
|
|
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:17 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 4.3 Placer Reporting
|
|
Phase 4.3 Placer Reporting | Checksum: 82956856
|
|
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:17 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 4.4 Final Placement Cleanup
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 4.4 Final Placement Cleanup | Checksum: 13d4dad90
|
|
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:17 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 13d4dad90
|
|
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:17 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Ending Placer Task | Checksum: 127086555
|
|
|
|
Time (s): cpu = 00:01:41 ; elapsed = 00:01:18 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
111 Infos, 244 Warnings, 108 Critical Warnings and 0 Errors encountered.
|
|
place_design completed successfully
|
|
place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:01:19 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing placer database...
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Common 17-1381] The checkpoint 'L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt
|
|
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.107 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
|
|
INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
|
|
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.115 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Command: route_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
|
Running DRC as a precondition to command route_design
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
|
|
INFO: [Common 17-14] Message 'Designutils 20-3303' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|
|
|
|
|
Starting Routing Task
|
|
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
|
Checksum: PlaceDB: 64002e0e ConstDB: 0 ShapeSum: c3083747 RouteDB: 0
|
|
|
|
Phase 1 Build RT Design
|
|
Phase 1 Build RT Design | Checksum: c0a504b9
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:54 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Post Restoration Checksum: NetGraph: 78fe1094 NumContArr: 47a6f425 Constraints: 0 Timing: 0
|
|
|
|
Phase 2 Router Initialization
|
|
|
|
Phase 2.1 Create Timer
|
|
Phase 2.1 Create Timer | Checksum: c0a504b9
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:54 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 2.2 Fix Topology Constraints
|
|
Phase 2.2 Fix Topology Constraints | Checksum: c0a504b9
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:54 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 2.3 Pre Route Cleanup
|
|
Phase 2.3 Pre Route Cleanup | Checksum: c0a504b9
|
|
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:54 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 2.4 Update Timing
|
|
Phase 2.4 Update Timing | Checksum: 11f8061a6
|
|
|
|
Time (s): cpu = 00:01:17 ; elapsed = 00:01:02 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-485.408| WHS=-0.469 | THS=-2533.917|
|
|
|
|
|
|
Phase 2.5 Update Timing for Bus Skew
|
|
|
|
Phase 2.5.1 Update Timing
|
|
Phase 2.5.1 Update Timing | Checksum: 845cdcbc
|
|
|
|
Time (s): cpu = 00:01:23 ; elapsed = 00:01:06 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-459.629| WHS=N/A | THS=N/A |
|
|
|
|
Phase 2.5 Update Timing for Bus Skew | Checksum: acde58b7
|
|
|
|
Time (s): cpu = 00:01:23 ; elapsed = 00:01:06 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 2 Router Initialization | Checksum: abf58de8
|
|
|
|
Time (s): cpu = 00:01:23 ; elapsed = 00:01:06 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 3 Initial Routing
|
|
Phase 3 Initial Routing | Checksum: 120fa6f91
|
|
|
|
Time (s): cpu = 00:01:38 ; elapsed = 00:01:14 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 4 Rip-up And Reroute
|
|
|
|
Phase 4.1 Global Iteration 0
|
|
Number of Nodes with overlaps = 1944
|
|
Number of Nodes with overlaps = 135
|
|
Number of Nodes with overlaps = 0
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.540 | TNS=-1268.527| WHS=N/A | THS=N/A |
|
|
|
|
Phase 4.1 Global Iteration 0 | Checksum: 164e52bf8
|
|
|
|
Time (s): cpu = 00:01:58 ; elapsed = 00:01:29 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 4.2 Global Iteration 1
|
|
Number of Nodes with overlaps = 48
|
|
Number of Nodes with overlaps = 6
|
|
Number of Nodes with overlaps = 0
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.540 | TNS=-1240.542| WHS=N/A | THS=N/A |
|
|
|
|
Phase 4.2 Global Iteration 1 | Checksum: 1abbd659a
|
|
|
|
Time (s): cpu = 00:02:00 ; elapsed = 00:01:31 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 4 Rip-up And Reroute | Checksum: 1abbd659a
|
|
|
|
Time (s): cpu = 00:02:00 ; elapsed = 00:01:31 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 5 Delay and Skew Optimization
|
|
|
|
Phase 5.1 Delay CleanUp
|
|
|
|
Phase 5.1.1 Update Timing
|
|
Phase 5.1.1 Update Timing | Checksum: 1772bf17a
|
|
|
|
Time (s): cpu = 00:02:01 ; elapsed = 00:01:32 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.540 | TNS=-1174.631| WHS=N/A | THS=N/A |
|
|
|
|
Number of Nodes with overlaps = 0
|
|
Phase 5.1 Delay CleanUp | Checksum: 2a4195bb6
|
|
|
|
Time (s): cpu = 00:02:03 ; elapsed = 00:01:33 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 5.2 Clock Skew Optimization
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 2a4195bb6
|
|
|
|
Time (s): cpu = 00:02:03 ; elapsed = 00:01:33 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 5 Delay and Skew Optimization | Checksum: 2a4195bb6
|
|
|
|
Time (s): cpu = 00:02:03 ; elapsed = 00:01:33 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 6 Post Hold Fix
|
|
|
|
Phase 6.1 Hold Fix Iter
|
|
|
|
Phase 6.1.1 Update Timing
|
|
Phase 6.1.1 Update Timing | Checksum: 2a815ea58
|
|
|
|
Time (s): cpu = 00:02:05 ; elapsed = 00:01:34 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.540 | TNS=-1093.679| WHS=-0.488 | THS=-1.943 |
|
|
|
|
|
|
Phase 6.1.2 Lut RouteThru Assignment for hold
|
|
Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: 14410cf63
|
|
|
|
Time (s): cpu = 00:02:06 ; elapsed = 00:01:35 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 6.1 Hold Fix Iter | Checksum: 14410cf63
|
|
|
|
Time (s): cpu = 00:02:06 ; elapsed = 00:01:35 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 6.2 Additional Hold Fix
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.540 | TNS=-1093.679| WHS=-0.488 | THS=-1.943 |
|
|
|
|
Phase 6.2 Additional Hold Fix | Checksum: 169cc8269
|
|
|
|
Time (s): cpu = 00:02:09 ; elapsed = 00:01:37 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Phase 6 Post Hold Fix | Checksum: 2a67d4384
|
|
|
|
Time (s): cpu = 00:02:10 ; elapsed = 00:01:38 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 7 Route finalize
|
|
|
|
Router Utilization Summary
|
|
Global Vertical Routing Utilization = 2.1774 %
|
|
Global Horizontal Routing Utilization = 2.77472 %
|
|
Routable Net Status*
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|
Run report_route_status for detailed report.
|
|
Number of Failed Nets = 0
|
|
Number of Unrouted Nets = 0
|
|
Number of Partially Routed Nets = 0
|
|
Number of Node Overlaps = 0
|
|
|
|
Congestion Report
|
|
North Dir 1x1 Area, Max Cong = 50.4505%, No Congested Regions.
|
|
South Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions.
|
|
East Dir 1x1 Area, Max Cong = 60.2941%, No Congested Regions.
|
|
West Dir 1x1 Area, Max Cong = 58.8235%, No Congested Regions.
|
|
|
|
------------------------------
|
|
Reporting congestion hotspots
|
|
------------------------------
|
|
Direction: North
|
|
----------------
|
|
Congested clusters found at Level 0
|
|
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
|
Direction: South
|
|
----------------
|
|
Congested clusters found at Level 0
|
|
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
|
Direction: East
|
|
----------------
|
|
Congested clusters found at Level 0
|
|
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
|
Direction: West
|
|
----------------
|
|
Congested clusters found at Level 0
|
|
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
|
|
|
Phase 7 Route finalize | Checksum: 1d2924cb8
|
|
|
|
Time (s): cpu = 00:02:10 ; elapsed = 00:01:39 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 8 Verifying routed nets
|
|
|
|
Verification completed successfully
|
|
Phase 8 Verifying routed nets | Checksum: 1d2924cb8
|
|
|
|
Time (s): cpu = 00:02:10 ; elapsed = 00:01:39 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Phase 9 Depositing Routes
|
|
Phase 9 Depositing Routes | Checksum: 184646891
|
|
|
|
Time (s): cpu = 00:02:12 ; elapsed = 00:01:40 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
WARNING: [Route 35-419] Router was unable to fix hold violation on pin design_1_i/adc_read_0/inst/fifo_din[6]_i_1/I2 driven by global clock buffer BUFGCTRL_X0Y20.
|
|
Resolution: Run report_timing_summary to analyze the hold violations.
|
|
WARNING: [Route 35-419] Router was unable to fix hold violation on pin design_1_i/adc_read_0/inst/fifo_din[3]_i_1/I2 driven by global clock buffer BUFGCTRL_X0Y20.
|
|
Resolution: Run report_timing_summary to analyze the hold violations.
|
|
|
|
Phase 10 Post Router Timing
|
|
|
|
Phase 10.1 Update Timing
|
|
Phase 10.1 Update Timing | Checksum: 22eb9ea50
|
|
|
|
Time (s): cpu = 00:02:14 ; elapsed = 00:01:41 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=-3.540 | TNS=-1093.679| WHS=-0.488 | THS=-1.943 |
|
|
|
|
WARNING: [Route 35-328] Router estimated timing not met.
|
|
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
|
|
Phase 10 Post Router Timing | Checksum: 22eb9ea50
|
|
|
|
Time (s): cpu = 00:02:14 ; elapsed = 00:01:42 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Route 35-16] Router Completed Successfully
|
|
|
|
Time (s): cpu = 00:02:14 ; elapsed = 00:01:42 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
|
|
Routing Is Done.
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
132 Infos, 347 Warnings, 108 Critical Warnings and 0 Errors encountered.
|
|
route_design completed successfully
|
|
route_design: Time (s): cpu = 00:02:18 ; elapsed = 00:01:44 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Writing placer database...
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [Common 17-1381] The checkpoint 'L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
|
|
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|
INFO: [Coretcl 2-168] The results of DRC are in file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.runs/impl_1/design_1_wrapper_drc_routed.rpt.
|
|
report_drc completed successfully
|
|
INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
|
|
Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
INFO: [DRC 23-133] Running Methodology with 2 threads
|
|
INFO: [Coretcl 2-1520] The results of Report Methodology are in file L:/PersonalProjects/Xilinx/SpectrumAnalyzer_FFT_windows/SpectrumAnalyzer_FFT_windows.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt.
|
|
report_methodology completed successfully
|
|
report_methodology: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
|
|
Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
Running Vector-less Activity Propagation...
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
|
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
|
|
144 Infos, 348 Warnings, 111 Critical Warnings and 0 Errors encountered.
|
|
report_power completed successfully
|
|
report_power: Time (s): cpu = 00:00:14 ; elapsed = 00:00:08 . Memory (MB): peak = 2928.855 ; gain = 0.000
|
|
INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
|
|
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
|
|
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|
CRITICAL WARNING: [Timing 38-249] Generated clock design_1_i/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O.
|
|
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
|
|
INFO: [Common 17-206] Exiting Vivado at Thu Nov 24 17:13:56 2022...
|
|
|
|
*** Running vivado
|
|
with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
|
|
|
|
|
|
****** Vivado v2018.3 (64-bit)
|
|
**** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
|
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
|
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|
|
|
source design_1_wrapper.tcl -notrace
|
|
Command: open_checkpoint design_1_wrapper_routed.dcp
|
|
|
|
Starting open_checkpoint Task
|
|
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 266.426 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 2180 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
|
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
|
INFO: [Timing 38-479] Binary timing data restore complete.
|
|
INFO: [Project 1-856] Restoring constraints from binary archive.
|
|
INFO: [Project 1-853] Binary constraint restore complete.
|
|
Reading XDEF placement.
|
|
Reading placer database...
|
|
Reading XDEF routing.
|
|
Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1645.496 ; gain = 25.395
|
|
Restored from archive | CPU: 4.000000 secs | Memory: 0.000000 MB |
|
|
Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1645.496 ; gain = 25.395
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1645.496 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 284 instances were transformed.
|
|
CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 212 instances
|
|
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 59 instances
|
|
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 10 instances
|
|
SRLC32E => SRL16E: 3 instances
|
|
|
|
INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3 (64-bit) build 2405991
|
|
open_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 1645.496 ; gain = 1379.070
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/v_axi4s_vid_out_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/axi_vdma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc1/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc1/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc1/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc1/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
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|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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Command: write_bitstream -force design_1_wrapper.bit
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Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
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Running DRC as a precondition to command write_bitstream
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'T:/AdvanceSoftwares/Xilinx2018/Vivado/2018.3/data/ip'.
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INFO: [DRC 23-27] Running DRC with 2 threads
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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WARNING: [Designutils 20-3303] unexpected site type 'IOPAD' in HDPYFinalizeIO
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INFO: [Common 17-14] Message 'Designutils 20-3303' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
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WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
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WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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|
WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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|
WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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|
WARNING: [DRC DPIP-1] Input pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 input design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-1] PREG Output pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 output design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/adc_read_0/inst/adc_conversion_f0/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/direct_fft_0/inst/imaginary_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[0].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC DPOP-2] MREG Output pipelining: DSP design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1 multiplier stage design_1_i/direct_fft_0/inst/real_2/U0/i_synth/MULT.OP/MULT/MULT_GEN_VARIANT.FIX_MULT/MULT/gDSP.gDSP_only.iDSP/use_prim.appDSP48[0].bppDSP48[1].use_dsp.use_dsp48e1.iDSP48E1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/interrupt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/left_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/right_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENARDEN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ENBWREN (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/direct_fft_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has an input control pin design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/WEA[0] (net: design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/p_17_out) which is driven by a register (design_1_i/direct_fft_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[11] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[9]) which is driven by a register (design_1_i/window_0/inst/addra_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[12] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[10]) which is driven by a register (design_1_i/window_0/inst/addra_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[13] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[11]) which is driven by a register (design_1_i/window_0/inst/addra_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram/ADDRARDADDR[14] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_init.ram/addra[12]) which is driven by a register (design_1_i/window_0/inst/addra_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ENARDEN (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/adc_read_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/ENBWREN (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0[0]) which is driven by a register (design_1_i/adc_read_0/inst/rd_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/WEA[0] (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/adc_read_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram has an input control pin design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram/WEA[1] (net: design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (design_1_i/adc_read_0/inst/wr_en_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/interrupt_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/left_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (design_1_i/key_ec11_0/inst/u_ec11_encoder/right_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[10] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[9]) which is driven by a register (design_1_i/window_0/inst/addra_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[11] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[10]) which is driven by a register (design_1_i/window_0/inst/addra_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[12] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[11]) which is driven by a register (design_1_i/window_0/inst/addra_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[13] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[12]) which is driven by a register (design_1_i/window_0/inst/addra_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[2] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[1]) which is driven by a register (design_1_i/window_0/inst/addra_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[3] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[2]) which is driven by a register (design_1_i/window_0/inst/addra_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[4] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[3]) which is driven by a register (design_1_i/window_0/inst/addra_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[5] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[4]) which is driven by a register (design_1_i/window_0/inst/addra_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[6] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[5]) which is driven by a register (design_1_i/window_0/inst/addra_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[7] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[6]) which is driven by a register (design_1_i/window_0/inst/addra_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[8] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[7]) which is driven by a register (design_1_i/window_0/inst/addra_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram has an input control pin design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram/ADDRARDADDR[9] (net: design_1_i/window_0/inst/rom_win_blackman/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/addra[8]) which is driven by a register (design_1_i/window_0/inst/addra_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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WARNING: [DRC RTSTAT-10] No routable loads: 29 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, design_1_i/direct_fft_0/inst/fifo_f1/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, design_1_i/adc_read_0/inst/fifo_generator_f0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 27 listed).
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/floating_add_abs1/U0/i_synth/ADDSUB_OP.ADDSUB/SPEED_OP.DSP.OP/DSP48E1_BODY.NORM_RND/FULL_USAGE_DSP.SHIFT_RND/DSP: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[1].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[0].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[1].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[1].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[1].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[0].appDSP[0].bppDSP[1].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[0].u_l[1].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/has_TW_mult.MULT/i_cmpy/four_mult_structure.use_dsp.i_dsp/re_im/use_DSP48.qDSP[1].appDSP[0].bppDSP[1].u_l[0].use_dsp48e1.dsp: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/hasbf2.FB_2.BF_2/MEM/blk_ram.use_bram_only.mem/depths_3to9.ram_loop[0].use_RAMB18.SDP_RAMB18E1_36x512) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[1].natural_order_input.PE/hasbf2.FB_2.BF_2/MEM/blk_ram.use_bram_only.mem/depths_3to9.ram_loop[1].use_RAMB18.SDP_RAMB18E1_36x512) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/FB_1.BF_1/MEM/blk_ram.use_bram_only.mem/depths_3to9.ram_loop[0].use_RAMB18.SDP_RAMB18E1_36x512) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/FB_1.BF_1/MEM/blk_ram.use_bram_only.mem/depths_3to9.ram_loop[1].use_RAMB18.SDP_RAMB18E1_36x512) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/hasbf2.FB_2.BF_2/MEM/blk_ram.use_bram_only.mem/depths_3to9.ram_loop[0].use_RAMB18.SDP_RAMB18E1_36x512) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (design_1_i/direct_fft_0/inst/xfft_fft1/U0/i_synth/xfft_inst/floating_point.xfft_inst/fft/non_floating_point.arch_d.xfft_inst/pe_gen[2].natural_order_input.PE/hasbf2.FB_2.BF_2/MEM/blk_ram.use_bram_only.mem/depths_3to9.ram_loop[1].use_RAMB18.SDP_RAMB18E1_36x512) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (design_1_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [DRC REQP-1725] DSP_Abus_sign_bit_alert: design_1_i/direct_fft_0/inst/floating_add_abs1/U0/i_synth/ADDSUB_OP.ADDSUB/SPEED_OP.DSP.OP/DSP48E1_BODY.ALIGN_ADD/DSP2/DSP: When using the PreAdder and USE_DPORT is TRUE, the A operand should be restricted to 24 bit two's complement (and sign extended) to avoid over/underflow in the pre-add stage.
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INFO: [Vivado 12-3199] DRC finished with 0 Errors, 70 Warnings, 29 Advisories
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INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
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INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
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Loading data files...
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Loading site data...
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Loading route data...
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Processing options...
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Creating bitmap...
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Creating bitstream...
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Writing bitstream ./design_1_wrapper.bit...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
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INFO: [Common 17-83] Releasing license: Implementation
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63 Infos, 170 Warnings, 0 Critical Warnings and 0 Errors encountered.
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write_bitstream completed successfully
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write_bitstream: Time (s): cpu = 00:01:24 ; elapsed = 00:01:02 . Memory (MB): peak = 2336.562 ; gain = 691.066
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INFO: [Common 17-206] Exiting Vivado at Thu Nov 24 17:15:54 2022...
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