917 lines
51 KiB
Plaintext
917 lines
51 KiB
Plaintext
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<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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|
|
<File Path="$PPRDIR/win_blackman.coe">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<Config>
|
||
|
|
<Option Name="DesignMode" Val="RTL"/>
|
||
|
|
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||
|
|
<Filter Type="Constrs"/>
|
||
|
|
<File Path="$PSRCDIR/constrs_1/hdmi7035.xdc">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../SpectrumAnalyzer4/SpectrumAnalyzer4.srcs/constrs_1/hdmi7035.xdc"/>
|
||
|
|
<Attr Name="ImportTime" Val="1666865769"/>
|
||
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<Config>
|
||
|
|
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/hdmi7035.xdc"/>
|
||
|
|
<Option Name="ConstrsType" Val="XDC"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||
|
|
<Filter Type="Srcs"/>
|
||
|
|
<File Path="$PSRCDIR/sim_1/new/direct_fft_tb.v">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../SpectrumAnalyzer4/SpectrumAnalyzer4.srcs/sim_1/new/direct_fft_tb.v"/>
|
||
|
|
<Attr Name="ImportTime" Val="1666944657"/>
|
||
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<File Path="$PSRCDIR/sim_1/new/window_tb.v">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
||
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<File Path="$PPRDIR/../SpectrumAnalyzer4/direct_fft_tb_behav.wcfg">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<File Path="$PPRDIR/window_tb_behav.wcfg">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<Config>
|
||
|
|
<Option Name="DesignMode" Val="RTL"/>
|
||
|
|
<Option Name="TopModule" Val="direct_fft_tb"/>
|
||
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||
|
|
<Option Name="TransportPathDelay" Val="0"/>
|
||
|
|
<Option Name="TransportIntDelay" Val="0"/>
|
||
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
||
|
|
<Option Name="XSimWcfgFile" Val="$PPRDIR/../SpectrumAnalyzer4/direct_fft_tb_behav.wcfg"/>
|
||
|
|
<Option Name="XSimWcfgFile" Val="$PPRDIR/window_tb_behav.wcfg"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||
|
|
<Filter Type="Utils"/>
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_axi_smc1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_smc1_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_axi_smc1_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clk_wiz_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_clk_wiz_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_util_vector_logic_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_util_vector_logic_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_util_vector_logic_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_axi_smc_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_smc_2">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_axi_smc_2"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_gpio_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_axi_gpio_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_system_ila_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_system_ila_0_1">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_system_ila_0_1"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="dds_compiler_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_compiler_0">
|
||
|
|
<File Path="$PSRCDIR/sources_1/ip/dds_compiler_0/dds_compiler_0.xci">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
||
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../SpectrumAnalyzer4/SpectrumAnalyzer4.srcs/sources_1/ip/dds_compiler_0/dds_compiler_0.xci"/>
|
||
|
|
<Attr Name="ImportTime" Val="1666825865"/>
|
||
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="dds_compiler_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_key_ec11_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_key_ec11_0_1">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_key_ec11_0_1"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_xbar_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xbar_2">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_xbar_2"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_axi_dma_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_dma_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_axi_dma_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="fix_float_dds" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fix_float_dds">
|
||
|
|
<File Path="$PSRCDIR/sources_1/ip/fix_float_dds/fix_float_dds.xci">
|
||
|
|
<FileInfo>
|
||
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
||
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
||
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
||
|
|
</FileInfo>
|
||
|
|
</File>
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="fix_float_dds"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_adc_read_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_adc_read_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_adc_read_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_direct_fft_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_direct_fft_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_direct_fft_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_axi_gpio_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_gpio_1_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_axi_gpio_1_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_window_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_window_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_window_0_0"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
</FileSets>
|
||
|
|
<Simulators>
|
||
|
|
<Simulator Name="XSim">
|
||
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||
|
|
<Option Name="CompiledLib" Val="0"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="ModelSim">
|
||
|
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="Questa">
|
||
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="Riviera">
|
||
|
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="ActiveHDL">
|
||
|
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
</Simulators>
|
||
|
|
<Runs Version="1" Minor="10">
|
||
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z035ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_axi_smc1_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_smc1_0" Part="xc7z035ffg676-2" ConstrsSet="design_1_axi_smc1_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_smc1_0_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_0" Part="xc7z035ffg676-2" ConstrsSet="design_1_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_wiz_0_0_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_util_vector_logic_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_util_vector_logic_0_0" Part="xc7z035ffg676-2" ConstrsSet="design_1_util_vector_logic_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_util_vector_logic_0_0_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_axi_smc_2_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_smc_2" Part="xc7z035ffg676-2" ConstrsSet="design_1_axi_smc_2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_smc_2_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_gpio_0_0" Part="xc7z035ffg676-2" ConstrsSet="design_1_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_gpio_0_0_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_system_ila_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_system_ila_0_1" Part="xc7z035ffg676-2" ConstrsSet="design_1_system_ila_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_system_ila_0_1_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="dds_compiler_0_synth_1" Type="Ft3:Synth" SrcSet="dds_compiler_0" Part="xc7z035ffg676-2" ConstrsSet="dds_compiler_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_compiler_0_synth_1" IncludeInArchive="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||
|
|
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|
|
<Run Id="design_1_axi_dma_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z035ffg676-2" ConstrsSet="design_1_axi_dma_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_dma_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="fix_float_dds_impl_1" Type="Ft2:EntireDesign" Part="xc7z035ffg676-2" ConstrsSet="fix_float_dds" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fix_float_dds_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_adc_read_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z035ffg676-2" ConstrsSet="design_1_adc_read_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_adc_read_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_direct_fft_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z035ffg676-2" ConstrsSet="design_1_direct_fft_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_direct_fft_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_axi_gpio_1_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z035ffg676-2" ConstrsSet="design_1_axi_gpio_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_gpio_1_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_window_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z035ffg676-2" ConstrsSet="design_1_window_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_window_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||
|
|
<Desc>Default settings for Implementation.</Desc>
|
||
|
|
</StratHandle>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
</Run>
|
||
|
|
</Runs>
|
||
|
|
<Board/>
|
||
|
|
<DashboardSummary Version="1" Minor="0">
|
||
|
|
<Dashboards>
|
||
|
|
<Dashboard Name="default_dashboard">
|
||
|
|
<Gadgets>
|
||
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||
|
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||
|
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
</Gadgets>
|
||
|
|
</Dashboard>
|
||
|
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||
|
|
</Dashboards>
|
||
|
|
</DashboardSummary>
|
||
|
|
<BootPmcSettings Version="1" Minor="0">
|
||
|
|
<Parameters/>
|
||
|
|
</BootPmcSettings>
|
||
|
|
</Project>
|