添加接收板代码 可以使用的
parent
6762ed027b
commit
7aea7e6b24
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@ -77,7 +77,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
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<IsCurrentTarget>1</IsCurrentTarget>
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</OPTFL>
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<CpuCode>6</CpuCode>
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<CpuCode>255</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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@ -103,7 +103,7 @@
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<bEvRecOn>1</bEvRecOn>
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<bSchkAxf>0</bSchkAxf>
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<bTchkAxf>0</bTchkAxf>
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<nTsel>7</nTsel>
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<nTsel>8</nTsel>
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<sDll></sDll>
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<sDllPa></sDllPa>
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<sDlgDll></sDlgDll>
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@ -184,7 +184,6 @@
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<hadXRAM>0</hadXRAM>
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<uocXRam>0</uocXRam>
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<RvdsVP>2</RvdsVP>
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<RvdsMve>0</RvdsMve>
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<hadIRAM2>0</hadIRAM2>
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<hadIROM2>0</hadIROM2>
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<StupSel>8</StupSel>
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@ -1,6 +1,6 @@
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/*
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* Auto generated Run-Time-Environment Configuration File
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* Auto generated Run-Time-Environment Component Configuration File
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* *** Do not modify ! ***
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*
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* Project: 'PWM_DeadZone'
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@ -16,14 +16,9 @@
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*/
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#define CMSIS_device_header "M451Series.h"
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/* Nuvoton::Device:Driver:CLK:3.01.001 */
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#define RTE_Drivers_CLK /* Driver CLK */
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/* Nuvoton::Device:Driver:PWM:3.01.001 */
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#define RTE_Drivers_PWM /* Driver PWM */
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/* Nuvoton::Device:Driver:SYS:3.01.001 */
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#define RTE_Drivers_SYS /* Driver SYS */
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/* Nuvoton::Device:Driver:UART:3.01.001 */
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#define RTE_Drivers_UART /* Driver UART */
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#endif /* RTE_COMPONENTS_H */
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File diff suppressed because one or more lines are too long
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@ -77,7 +77,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
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<IsCurrentTarget>1</IsCurrentTarget>
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</OPTFL>
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<CpuCode>6</CpuCode>
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<CpuCode>255</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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@ -103,7 +103,7 @@
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<bEvRecOn>1</bEvRecOn>
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<bSchkAxf>0</bSchkAxf>
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<bTchkAxf>0</bTchkAxf>
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<nTsel>7</nTsel>
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<nTsel>8</nTsel>
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<sDll></sDll>
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<sDllPa></sDllPa>
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<sDlgDll></sDlgDll>
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@ -184,7 +184,6 @@
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<hadXRAM>0</hadXRAM>
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<uocXRam>0</uocXRam>
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<RvdsVP>2</RvdsVP>
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<RvdsMve>0</RvdsMve>
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<hadIRAM2>0</hadIRAM2>
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<hadIROM2>0</hadIROM2>
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<StupSel>8</StupSel>
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@ -1,6 +1,6 @@
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/*
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* Auto generated Run-Time-Environment Configuration File
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* Auto generated Run-Time-Environment Component Configuration File
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* *** Do not modify ! ***
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*
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* Project: 'OLED'
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@ -16,18 +16,11 @@
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*/
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#define CMSIS_device_header "M451Series.h"
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/* Nuvoton::Device:Driver:CLK:3.01.001 */
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#define RTE_Drivers_CLK /* Driver CLK */
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/* Nuvoton::Device:Driver:GPIO:3.01.001 */
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#define RTE_Drivers_GPIO /* Driver GPIO */
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/* Nuvoton::Device:Driver:I2C:3.01.001 */
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#define RTE_Drivers_I2C /* Driver I2C */
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/* Nuvoton::Device:Driver:SC:3.01.001 */
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#define RTE_Drivers_SC /* Driver SC */
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/* Nuvoton::Device:Driver:SYS:3.01.001 */
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#define RTE_Drivers_SYS /* Driver SYS */
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/* Nuvoton::Device:Driver:UART:3.01.001 */
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#define RTE_Drivers_UART /* Driver UART */
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#endif /* RTE_COMPONENTS_H */
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@ -0,0 +1,267 @@
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#include "M451Series.h"
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#include "24l01.h"
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#include "spi_hal.h"
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uchar Recv_Buf[32] = {0};
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uchar Send_Buf[32] = {0};
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char rfch = 45;
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unsigned short RxCnt = 0;
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unsigned char TxAddr[]={0x11,0x22,0x33,0x44,0x55};//????
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unsigned char RxAddr[]={0x11,0x22,0x33,0x44,0x55};//????
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enum NRF_Mode Curr_Mode = NRF_RX_Mode;
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void delay_s()
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{
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int z=0;
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for(z=0;z<250;z++)
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{}
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}
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void delay_mss()
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{
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int z = 0;
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for(z=0;z<5;z++)
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{
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delay_s();
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}
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}
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void NRF_Init(void)
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{
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}
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void NRF_SetUpInterrupt(void)
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{
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GPIO_SetMode(PB,BIT15,GPIO_MODE_INPUT);
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GPIO_EnableInt(PB,15,GPIO_INT_FALLING);
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NVIC->ISER[0]|=(0X01<<2);
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}
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int gRecvPkg = 0;
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//接收或者发送中断
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void EINT0_IRQHandler()
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{
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char trycnt = 5;
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gRecvPkg ++;
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delay_s();
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switch(Curr_Mode){
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//if now in rx mode mean data been receieved
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case NRF_RX_Mode:
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//PB9 = 0;
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while(trycnt > 0)
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{
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if(NRF24L01_RxPacket(Recv_Buf) == 0)
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{
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NRFSetTxMode();
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break;
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}
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trycnt --;
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}
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//nrf_write(FLUSH_RX,0xff);//清除RX FIFO寄存器
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//PB9 = 1;
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//read the buffer
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break;
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//if now in tx mode mean data been sent
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case NRF_TX_Mode:
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break;
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}
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PB->INTSRC |= BIT14;
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}
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void RX_Mode(void)
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{
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char sta;
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sta = nrf_read(STATUS);
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nrf_write(W_REGISTER + STATUS,sta);
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nrf_write(FLUSH_TX,0xff);
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nrf_write(FLUSH_RX,0xff);
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PB13=0;
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Curr_Mode = NRF_RX_Mode;
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delay_s();
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nrf_writebuf(W_REGISTER + TX_ADDR,(uchar*)TxAddr,5);//写TX节点地址
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nrf_writebuf(W_REGISTER + RX_ADDR_P0,(uchar*)RxAddr,5); //设置TX节点地址,主要为了使能ACK
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nrf_write(W_REGISTER + SETUP_RETR,0x11);//设置自动重发间隔时间:500us + 86us;最大自动重发次数:10次
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nrf_write(W_REGISTER + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
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nrf_write(W_REGISTER + EN_RXADDR, 0x01); // Enable Pipe0
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nrf_write(W_REGISTER + RF_CH, rfch); // Select RF channel 40
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nrf_write(W_REGISTER + RX_PW_P0,RX_DATA_WITDH);
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//nrf_write(W_REGISTER+FEATURE, 0x20);
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nrf_write(W_REGISTER + RF_SETUP, 0x0f);
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nrf_write(W_REGISTER + CONFIG, 0x2f); // Set PWR_UP bit, enable CRC(2 bytes)
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delay_s();
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PB13=1;
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}
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void NRFSwitchMode(char mode)
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{
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static char ifinit = 0;
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//TX Mode
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if(mode == 1)
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{
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if (0 == ifinit)
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{
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NRFSetTxMode();
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ifinit = 1;
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return;
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}
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PB9 = 0;
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nrf_write(W_REGISTER + STATUS,0xff); //使能通道0的自动应答
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nrf_write(FLUSH_TX,0); //使能通道0的自动应答
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nrf_write(W_REGISTER + CONFIG,0xfe); //使能通道0的自动应答
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delay_s();
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PB9 = 1;
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}
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else
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{
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PB9 = 0;
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nrf_write(W_REGISTER+STATUS,0xff); //使能通道0的自动应答
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nrf_write(FLUSH_TX,0); //使能通道0的自动应答
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nrf_write(W_REGISTER + CONFIG,0xff); //使能通道0的自动应答
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delay_s();
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PB9 = 1;
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}
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}
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void NRFSetTxMode()
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{
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char sta;
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sta = nrf_read(STATUS);
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nrf_write(W_REGISTER + STATUS,sta);
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nrf_write(FLUSH_TX,0xff);
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nrf_write(FLUSH_RX,0xff);
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PB14 = 0;
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Curr_Mode = NRF_TX_Mode;
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delay_s();
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nrf_writebuf(W_REGISTER+TX_ADDR,(uchar*)TxAddr,5);//写TX节点地址
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nrf_writebuf(W_REGISTER+RX_ADDR_P0,(uchar*)RxAddr,5); //设置TX节点地址,主要为了使能ACK
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nrf_write(W_REGISTER+EN_AA,0x01); //使能通道0的自动应答
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nrf_write(W_REGISTER+EN_RXADDR,0x01); //使能通道0的接收地址
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nrf_write(W_REGISTER+SETUP_RETR,0x1a);//设置自动重发间隔时间:500us + 86us;最大自动重发次数:10次
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nrf_write(W_REGISTER+RF_CH,rfch); //设置RF通道为40
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nrf_write(W_REGISTER+RF_SETUP,0x0f); //设置TX发射参数,0db增益,2Mbps,低噪声增益开启
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nrf_write(W_REGISTER+CONFIG,0x0e); //配置基本工作模式的参数;PWR_UP,EN_CRC,16BIT_CRC,接收模式,开启所有中断
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delay_s();
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PB14 = 1;
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}
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//启动NRF24L01发送一次数据
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//txbuf:待发送数据首地址
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//返回值:发送完成状况
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unsigned char NRF24L01_TxPacket(unsigned char *txbuf)
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{
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unsigned char sta;
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PB9=0;
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delay_s();
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nrf_writebuf(W_TX_PAYLOAD,txbuf,TX_DATA_WITDH);//写数据到TX BUF 32个字节
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PB9=1;
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sta=nrf_read(STATUS); //读取状态寄存器的值
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nrf_write(W_REGISTER+STATUS,sta); //清除TX_DS或MAX_RT中断标志
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if(sta&0x10)//达到最大重发次数
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{
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nrf_wf(FLUSH_TX);//清除TX FIFO寄存器
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nrf_write(W_REGISTER+STATUS,sta); //清除TX_DS或MAX_RT中断标志
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sta=nrf_read(STATUS); //读取状态寄存器的值
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return 0x10;
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}
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if(sta&0x20)//发送完成
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{
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return 0;
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}
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return 0xff;//其他原因发送失败
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}
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unsigned char NrfDump()
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{
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char ret = 0;
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ret=nrf_read(EN_AA);
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delay_s();
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ret=nrf_read(EN_RXADDR);
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delay_s();
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ret=nrf_read(RF_CH);
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delay_s();
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ret=nrf_read(RX_PW_P0);
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delay_s();
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ret=nrf_read(RF_SETUP);
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delay_s();
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ret=nrf_read(CONFIG);
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delay_s();
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ret=nrf_read(CD);
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delay_s();
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ret=nrf_read(STATUS);
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delay_s();
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return ret;
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}
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unsigned char NRF24L01_Read_Buf(unsigned char reg,unsigned char *pBuf,unsigned char len)
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{
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unsigned char status,u8_ctr;
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spi_enable();
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status=spi_send(reg);
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for(u8_ctr=0;u8_ctr<len;u8_ctr++)
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pBuf[u8_ctr]= spi_read();
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spi_disable();
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return status;
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}
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//载波监听
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unsigned char NRF24L01_CD_Detect()
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{
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short ret = 0;
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int x = 255;
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int i = 0;
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unsigned char sum = 0;
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for(i=0;i<x;i++){
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ret=nrf_read(CD);
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sum+=ret;
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}
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return sum;
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}
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void NRF24L01_Monitor()
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{
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char ret = nrf_read(STATUS);
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ret = nrf_read(CONFIG);
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ret = nrf_read(RF_SETUP);
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if(ret & 0x10)
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{
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nrf_write(W_REGISTER+STATUS,ret); //清除TX_DS或MAX_RT中断标志
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}
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}
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short NRF24L01_RxPacket(unsigned char *rxbuf)
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{
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unsigned char sta;
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sta = nrf_read(STATUS); //读取状态寄存器的<E599A8>
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if(sta&0x40)//接收到数据
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{
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NRF24L01_Read_Buf(0x61,rxbuf,RX_DATA_WITDH);//读取数据
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RxCnt ++;
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//nrf_write(W_REGISTER+STATUS,sta); //清除TX_DS或MAX_RT中断标志
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return 0;
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}
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if(sta & 0x20) //如果该中断已经有数据发送了
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{
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nrf_write(W_REGISTER+STATUS,sta); //清除TX_DS或MAX_RT中断标志
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return -1;
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}
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return -1;//没收到任何数据
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}
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@ -0,0 +1,64 @@
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#ifndef __NRF__
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#define __NRF__
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#include "spi_hal.h"
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#define uchar unsigned char
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/*******************************************************/
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#define CONFIG 0x00
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#define TX_DATA_WITDH 32//??????1???
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#define RX_DATA_WITDH 32 //??????1???
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/*******************?????***************************/
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#define R_REGISTER 0x00//???????
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#define W_REGISTER 0x20//??????
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#define R_RX_PAYLOAD 0x61//??RX????
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#define W_TX_PAYLOAD 0xa0//?TX????
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#define FLUSH_TX 0xe1//??TXFIFO???
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#define FLUSH_RX 0xe2//??RXFIFO???
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#define REUSE_TX_PL 0xe3//???????????
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#define NOP 0xff//???
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/******************?????****************************/
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#define EN_AA 0x01//??????
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#define EN_RXADDR 0x02//??????0-5???
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#define SETUP_AW 0x03//??????????3-5
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#define SETUP_RETR 0x04//??????
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#define RF_CH 0x05//??????
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#define RF_SETUP 0x06//?????
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#define STATUS 0x07//?????
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#define OBSERVE_TX 0x08//???????
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#define CD 0x09//??
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#define RX_ADDR_P0 0x0a//????0????
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#define RX_ADDR_P1 0x0b//????1????
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#define RX_ADDR_P2 0x0c//????2????
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#define RX_ADDR_P3 0x0d//????3????
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#define RX_ADDR_P4 0x0e//????4????
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#define RX_ADDR_P5 0x0f//????5????
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#define TX_ADDR 0x10//????
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#define RX_PW_P0 0x11//P0????????
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#define RX_PW_P1 0x12//P1????????
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#define RX_PW_P2 0x13//P2????????
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#define RX_PW_P3 0x14//P3????????
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#define RX_PW_P4 0x15//P4????????
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#define RX_PW_P5 0x16//P5????????
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#define FIFO_STATUS 0x17//FIFO?????
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#define FEATURE 0X1D
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enum NRF_Mode {
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NRF_RX_Mode = 1,
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NRF_TX_Mode =2
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};
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void NRF24L01_Monitor(void);
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void RX_Mode(void);
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unsigned char NRF24L01_CD_Detect(void);
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unsigned char NRF24L01_Read_Buf(unsigned char reg,unsigned char *pBuf,unsigned char len);
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short NRF24L01_RxPacket(unsigned char *rxbuf);
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unsigned char NRF24L01_TxPacket(unsigned char *txbuf);
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void NRFSetTxMode(void);
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void RX_Mode(void);
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unsigned char NrfDump();
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extern uchar Recv_Buf[32];
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extern uchar Send_Buf[32];
|
||||
extern enum NRF_Mode Curr_Mode;
|
||||
extern int gRecvPkg;
|
||||
#endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
|
||||
|
||||
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
|
||||
<events>
|
||||
</events>
|
||||
|
||||
</component_viewer>
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -0,0 +1,17 @@
|
|||
--cpu=Cortex-M4.fp
|
||||
".\objects\main.o"
|
||||
".\objects\24l01.o"
|
||||
".\objects\spi_hal.o"
|
||||
".\objects\interrupt.o"
|
||||
".\objects\clk.o"
|
||||
".\objects\gpio.o"
|
||||
".\objects\pwm.o"
|
||||
".\objects\spi.o"
|
||||
".\objects\sys.o"
|
||||
".\objects\retarget.o"
|
||||
".\objects\startup_m451series.o"
|
||||
".\objects\system_m451series.o"
|
||||
--strict --scatter ".\Objects\roboticarm_controller.sct"
|
||||
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
|
||||
--info sizes --info totals --info unused --info veneers
|
||||
--list ".\Listings\roboticarm_controller.map" -o .\Objects\roboticarm_controller.axf
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00008000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,678 @@
|
|||
/**************************************************************************//**
|
||||
* @file retarget.c
|
||||
* @version V3.00
|
||||
* $Revision: 13 $
|
||||
* $Date: 15/08/11 10:26a $
|
||||
* @brief M451 Series Debug Port and Semihost Setting Source File
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include "M451Series.h"
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
#else
|
||||
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
|
||||
#pragma import _printf_widthprec
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Global variables */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
#endif
|
||||
FILE __stdout;
|
||||
FILE __stdin;
|
||||
|
||||
enum { r0, r1, r2, r3, r12, lr, pc, psr};
|
||||
|
||||
/**
|
||||
* @brief Helper function to dump register while hard fault occurred
|
||||
* @param[in] stack pointer points to the dumped registers in SRAM
|
||||
* @return None
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*/
|
||||
static void stackDump(uint32_t stack[])
|
||||
{
|
||||
printf("r0 = 0x%x\n", stack[r0]);
|
||||
printf("r1 = 0x%x\n", stack[r1]);
|
||||
printf("r2 = 0x%x\n", stack[r2]);
|
||||
printf("r3 = 0x%x\n", stack[r3]);
|
||||
printf("r12 = 0x%x\n", stack[r12]);
|
||||
printf("lr = 0x%x\n", stack[lr]);
|
||||
printf("pc = 0x%x\n", stack[pc]);
|
||||
printf("psr = 0x%x\n", stack[psr]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Hard fault handler
|
||||
* @param[in] stack pointer points to the dumped registers in SRAM
|
||||
* @return None
|
||||
* @details Replace while(1) at the end of this function with chip reset if WDT is not enabled for end product
|
||||
*/
|
||||
void Hard_Fault_Handler(uint32_t stack[])
|
||||
{
|
||||
printf("In Hard Fault Handler\n");
|
||||
|
||||
stackDump(stack);
|
||||
// Replace while(1) with chip reset if WDT is not enabled for end product
|
||||
while(1);
|
||||
//SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Routine to write a char */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
/* The static buffer is used to speed up the semihost */
|
||||
static char g_buf[16];
|
||||
static char g_buf_len = 0;
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
void SH_End(void)
|
||||
{
|
||||
asm("MOVS R0,#1 \n" //; Set return value to 1
|
||||
"BX lr \n" //; Return
|
||||
);
|
||||
}
|
||||
|
||||
void SH_ICE(void)
|
||||
{
|
||||
asm("CMP R2,#0 \n"
|
||||
"BEQ SH_End \n"
|
||||
"STR R0,[R2] \n" //; Save the return value to *pn32Out_R0
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
|
||||
"B SH_ICE \n"
|
||||
"SH_HardFault: \n" //; Captured by HardFault
|
||||
"MOVS R0,#0 \n" //; Set return value to 0
|
||||
"BX lr \n" //; Return
|
||||
);
|
||||
|
||||
return 1; //; Return 1 when it is trap by ICE
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LR value and branch to Hard_Fault_Handler function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get LR value and branch to Hard_Fault_Handler function.
|
||||
*/
|
||||
void Get_LR_and_Branch(void)
|
||||
{
|
||||
asm("MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get MSP value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void Stack_Use_MSP(void)
|
||||
{
|
||||
asm("MRS R0, MSP \n" //; read MSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get stack pointer value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void HardFault_Handler_Ret(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n" //; check LR bit 2
|
||||
"BEQ Stack_Use_MSP \n" //; stack use MSP
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is implemented to support semihost
|
||||
* @param None
|
||||
* @returns None
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void SP_Read_Ready(void)
|
||||
{
|
||||
asm("LDR R1, [R0, #24] \n" //; Get previous PC
|
||||
"LDRH R3, [R1] \n" //; Get instruction
|
||||
"LDR R2, [pc, #8] \n" //; The special BKPT instruction
|
||||
"CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
|
||||
"BNE HardFault_Handler_Ret \n" //; Not BKPT
|
||||
"ADDS R1, #4 \n" //; Skip BKPT and next line
|
||||
"STR R1, [R0, #24] \n" //; Save previous PC
|
||||
"BX lr \n" //; Return
|
||||
"DCD 0xBEAB \n" //; BKPT instruction code
|
||||
"B HardFault_Handler_Ret \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get stack pointer value and branch to Get_LR_and_Branch function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
|
||||
*/
|
||||
void SP_is_PSP(void)
|
||||
{
|
||||
asm(
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler (void)
|
||||
{
|
||||
asm("MOV R0, lr \n"
|
||||
"LSLS R0, #29 \n" //; Check bit 2
|
||||
"BMI SP_is_PSP \n" //; previous stack is PSP
|
||||
"MRS R0, MSP \n" //; previous stack is MSP, read MSP
|
||||
"B SP_Read_Ready \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
* @param None
|
||||
* @returns None
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOV R0, LR
|
||||
LSLS R0, #29 //; Check bit 2
|
||||
BMI SP_is_PSP //; previous stack is PSP
|
||||
MRS R0, MSP //; previous stack is MSP, read MSP
|
||||
B SP_Read_Ready
|
||||
SP_is_PSP
|
||||
MRS R0, PSP //; Read PSP
|
||||
|
||||
SP_Read_Ready
|
||||
LDR R1, [R0, #24] //; Get previous PC
|
||||
LDRH R3, [R1] //; Get instruction
|
||||
LDR R2, =0xBEAB //; The special BKPT instruction
|
||||
CMP R3, R2 //; Test if the instruction at previous PC is BKPT
|
||||
BNE HardFault_Handler_Ret //; Not BKPT
|
||||
|
||||
ADDS R1, #4 //; Skip BKPT and next line
|
||||
STR R1, [R0, #24] //; Save previous PC
|
||||
|
||||
BX LR //; Return
|
||||
HardFault_Handler_Ret
|
||||
|
||||
/* TODO: Implement your own hard fault handler here. */
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1 //; check LR bit 2
|
||||
BEQ Stack_Use_MSP //; stack use MSP
|
||||
MRS R0, PSP ;stack use PSP //; stack use PSP, read PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP ; stack use MSP //; read MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR ; LR current value //; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
|
||||
BX R2
|
||||
|
||||
B .
|
||||
|
||||
ALIGN
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
BKPT 0xAB //; Wait ICE or HardFault
|
||||
//; ICE will step over BKPT directly
|
||||
//; HardFault will step BKPT and the next line
|
||||
B SH_ICE
|
||||
|
||||
SH_HardFault //; Captured by HardFault
|
||||
MOVS R0, #0 //; Set return value to 0
|
||||
BX lr //; Return
|
||||
|
||||
SH_ICE //; Captured by ICE
|
||||
//; Save return value
|
||||
CMP R2, #0
|
||||
BEQ SH_End
|
||||
STR R0, [R2] //; Save the return value to *pn32Out_R0
|
||||
|
||||
SH_End
|
||||
MOVS R0, #1 //; Set return value to 1
|
||||
BX lr //; Return
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
void Get_LR_and_Branch(void)
|
||||
{
|
||||
asm("MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
}
|
||||
|
||||
void Stack_Use_MSP(void)
|
||||
{
|
||||
asm("MRS R0, MSP \n" //; read MSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n" //; check LR bit 2
|
||||
"BEQ Stack_Use_MSP \n" //; stack use MSP
|
||||
"MRS R0, PSP \n" //; stack use PSP, read PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function extracts the location of stack frame and passes it to Hard_Fault_Handler function as a pointer
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1 //; check LR bit 2
|
||||
BEQ Stack_Use_MSP //; stack use MSP
|
||||
MRS R0, PSP //; stack use PSP, read PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP //; read MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR //; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
|
||||
BX R2
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Routine to send a char
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns Send value from UART debug port
|
||||
*
|
||||
* @details Send a target char to UART debug port .
|
||||
*/
|
||||
#ifndef NONBLOCK_PRINTF
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
|
||||
DEBUG_PORT->DAT = ch;
|
||||
if(ch == '\n')
|
||||
{
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
DEBUG_PORT->DAT = '\r';
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/* Non-block implement of send char */
|
||||
#define BUF_SIZE 2048
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
static uint8_t u8Buf[BUF_SIZE] = {0};
|
||||
static int32_t i32Head = 0;
|
||||
static int32_t i32Tail = 0;
|
||||
int32_t i32Tmp;
|
||||
|
||||
/* Only flush the data in buffer to UART when ch == 0 */
|
||||
if(ch)
|
||||
{
|
||||
// Push char
|
||||
i32Tmp = i32Head+1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
if(i32Tmp != i32Tail)
|
||||
{
|
||||
u8Buf[i32Head] = ch;
|
||||
i32Head = i32Tmp;
|
||||
}
|
||||
|
||||
if(ch == '\n')
|
||||
{
|
||||
i32Tmp = i32Head+1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
if(i32Tmp != i32Tail)
|
||||
{
|
||||
u8Buf[i32Head] = '\r';
|
||||
i32Head = i32Tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(i32Tail == i32Head)
|
||||
return;
|
||||
}
|
||||
|
||||
// pop char
|
||||
do
|
||||
{
|
||||
i32Tmp = i32Tail + 1;
|
||||
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
|
||||
|
||||
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) == 0)
|
||||
{
|
||||
DEBUG_PORT->DAT = u8Buf[i32Tail];
|
||||
i32Tail = i32Tmp;
|
||||
}
|
||||
else
|
||||
break; // FIFO full
|
||||
}while(i32Tail != i32Head);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Routine to send a char
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns Send value from UART debug port or semihost
|
||||
*
|
||||
* @details Send a target char to UART debug port or semihost.
|
||||
*/
|
||||
void SendChar(int ch)
|
||||
{
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
g_buf[g_buf_len++] = ch;
|
||||
g_buf[g_buf_len] = '\0';
|
||||
if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
|
||||
{
|
||||
/* Send the char */
|
||||
if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
|
||||
{
|
||||
g_buf_len = 0;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = 0; i < g_buf_len; i++)
|
||||
SendChar_ToUART(g_buf[i]);
|
||||
g_buf_len = 0;
|
||||
}
|
||||
}
|
||||
#else
|
||||
SendChar_ToUART(ch);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Routine to get a char
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns Get value from UART debug port or semihost
|
||||
*
|
||||
* @details Wait UART debug port or semihost to input a char.
|
||||
*/
|
||||
char GetChar(void)
|
||||
{
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# if defined (__CC_ARM)
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x101, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
{
|
||||
SH_DoCommand(0x07, 0, &nRet);
|
||||
return (char)nRet;
|
||||
}
|
||||
}
|
||||
# else
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x7, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
return (char)nRet;
|
||||
}
|
||||
# endif
|
||||
return (0);
|
||||
#else
|
||||
|
||||
while(1)
|
||||
{
|
||||
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0)
|
||||
{
|
||||
return (DEBUG_PORT->DAT);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check any char input from UART
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 1: No any char input
|
||||
* @retval 0: Have some char input
|
||||
*
|
||||
* @details Check UART RSR RX EMPTY or not to determine if any char input from UART
|
||||
*/
|
||||
|
||||
int kbhit(void)
|
||||
{
|
||||
return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0);
|
||||
}
|
||||
/**
|
||||
* @brief Check if debug message finished
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 1: Message is finished
|
||||
* @retval 0: Message is transmitting.
|
||||
*
|
||||
* @details Check if message finished (FIFO empty of debug port)
|
||||
*/
|
||||
|
||||
int IsDebugFifoEmpty(void)
|
||||
{
|
||||
return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief C library retargetting
|
||||
*
|
||||
* @param[in] ch Character to send to debug port.
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details Check if message finished (FIFO empty of debug port)
|
||||
*/
|
||||
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
SendChar(ch);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write character to stream
|
||||
*
|
||||
* @param[in] ch Character to be written. The character is passed as its int promotion.
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
|
||||
*
|
||||
* @returns If there are no errors, the same character that has been written is returned.
|
||||
* If an error occurs, EOF is returned and the error indicator is set (see ferror).
|
||||
*
|
||||
* @details Writes a character to the stream and advances the position indicator.\n
|
||||
* The character is written at the current position of the stream as indicated \n
|
||||
* by the internal position indicator, which is then advanced one character.
|
||||
*
|
||||
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
int fputc(int ch, FILE *stream)
|
||||
{
|
||||
SendChar(ch);
|
||||
return ch;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get character from UART debug port or semihosting input
|
||||
*
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
|
||||
*
|
||||
* @returns The character read from UART debug port or semihosting
|
||||
*
|
||||
* @details For get message from debug port or semihosting.
|
||||
*
|
||||
*/
|
||||
|
||||
int fgetc(FILE *stream)
|
||||
{
|
||||
return (GetChar());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check error indicator
|
||||
*
|
||||
* @param[in] stream Pointer to a FILE object that identifies the stream.
|
||||
*
|
||||
* @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
|
||||
* Otherwise, it returns a zero value.
|
||||
*
|
||||
* @details Checks if the error indicator associated with stream is set, returning a value different
|
||||
* from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
|
||||
*
|
||||
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
|
||||
*
|
||||
*/
|
||||
|
||||
int ferror(FILE *stream)
|
||||
{
|
||||
return EOF;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# ifdef __ICCARM__
|
||||
void __exit(int return_code)
|
||||
{
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
# else
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,376 @@
|
|||
;/******************************************************************************
|
||||
; * @file startup_M451Series.s
|
||||
; * @version V0.10
|
||||
; * $Revision: 5 $
|
||||
; * $Date: 14/12/24 10:20a $
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for M451 Series MCU
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||
;*****************************************************************************/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
; User may overwrite stack size setting by pre-defined symbol
|
||||
IF :LNOT: :DEF: Stack_Size
|
||||
Stack_Size EQU 0x00000400
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
IF :LNOT: :DEF: Heap_Size
|
||||
Heap_Size EQU 0x00000000
|
||||
ENDIF
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD BOD_IRQHandler ; 0: Brown Out detection
|
||||
DCD IRC_IRQHandler ; 1: Internal RC
|
||||
DCD PWRWU_IRQHandler ; 2: Power down wake up
|
||||
DCD RAMPE_IRQHandler ; 3: RAM parity error
|
||||
DCD CLKFAIL_IRQHandler ; 4: Clock detection fail
|
||||
DCD Default_Handler ; 5: Reserved
|
||||
DCD RTC_IRQHandler ; 6: Real Time Clock
|
||||
DCD TAMPER_IRQHandler ; 7: Tamper detection
|
||||
DCD WDT_IRQHandler ; 8: Watchdog timer
|
||||
DCD WWDT_IRQHandler ; 9: Window watchdog timer
|
||||
DCD EINT0_IRQHandler ; 10: External Input 0
|
||||
DCD EINT1_IRQHandler ; 11: External Input 1
|
||||
DCD EINT2_IRQHandler ; 12: External Input 2
|
||||
DCD EINT3_IRQHandler ; 13: External Input 3
|
||||
DCD EINT4_IRQHandler ; 14: External Input 4
|
||||
DCD EINT5_IRQHandler ; 15: External Input 5
|
||||
DCD GPA_IRQHandler ; 16: GPIO Port A
|
||||
DCD GPB_IRQHandler ; 17: GPIO Port B
|
||||
DCD GPC_IRQHandler ; 18: GPIO Port C
|
||||
DCD GPD_IRQHandler ; 19: GPIO Port D
|
||||
DCD GPE_IRQHandler ; 20: GPIO Port E
|
||||
DCD GPF_IRQHandler ; 21: GPIO Port F
|
||||
DCD SPI0_IRQHandler ; 22: SPI0
|
||||
DCD SPI1_IRQHandler ; 23: SPI1
|
||||
DCD BRAKE0_IRQHandler ; 24:
|
||||
DCD PWM0P0_IRQHandler ; 25:
|
||||
DCD PWM0P1_IRQHandler ; 26:
|
||||
DCD PWM0P2_IRQHandler ; 27:
|
||||
DCD BRAKE1_IRQHandler ; 28:
|
||||
DCD PWM1P0_IRQHandler ; 29:
|
||||
DCD PWM1P1_IRQHandler ; 30:
|
||||
DCD PWM1P2_IRQHandler ; 31:
|
||||
DCD TMR0_IRQHandler ; 32: Timer 0
|
||||
DCD TMR1_IRQHandler ; 33: Timer 1
|
||||
DCD TMR2_IRQHandler ; 34: Timer 2
|
||||
DCD TMR3_IRQHandler ; 35: Timer 3
|
||||
DCD UART0_IRQHandler ; 36: UART0
|
||||
DCD UART1_IRQHandler ; 37: UART1
|
||||
DCD I2C0_IRQHandler ; 38: I2C0
|
||||
DCD I2C1_IRQHandler ; 39: I2C1
|
||||
DCD PDMA_IRQHandler ; 40: Peripheral DMA
|
||||
DCD DAC_IRQHandler ; 41: DAC
|
||||
DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
|
||||
DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
|
||||
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
|
||||
DCD Default_Handler ; 45: Reserved
|
||||
DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
|
||||
DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
|
||||
DCD UART2_IRQHandler ; 48: UART2
|
||||
DCD UART3_IRQHandler ; 49: UART3
|
||||
DCD Default_Handler ; 50: Reserved
|
||||
DCD SPI2_IRQHandler ; 51: SPI2
|
||||
DCD Default_Handler ; 52: Reserved
|
||||
DCD USBD_IRQHandler ; 53: USB device
|
||||
DCD USBH_IRQHandler ; 54: USB host
|
||||
DCD USBOTG_IRQHandler ; 55: USB OTG
|
||||
DCD CAN0_IRQHandler ; 56: CAN0
|
||||
DCD Default_Handler ; 57: Reserved
|
||||
DCD SC0_IRQHandler ; 58:
|
||||
DCD Default_Handler ; 59: Reserved.
|
||||
DCD Default_Handler ; 60:
|
||||
DCD Default_Handler ; 61:
|
||||
DCD Default_Handler ; 62:
|
||||
DCD TK_IRQHandler ; 63:
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Select INV Type
|
||||
LDR R2, =0x40000200
|
||||
LDR R1, [R2]
|
||||
BIC R1, R1, #0x1000
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT IRC_IRQHandler [WEAK]
|
||||
EXPORT PWRWU_IRQHandler [WEAK]
|
||||
EXPORT RAMPE_IRQHandler [WEAK]
|
||||
EXPORT CLKFAIL_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT EINT2_IRQHandler [WEAK]
|
||||
EXPORT EINT3_IRQHandler [WEAK]
|
||||
EXPORT EINT4_IRQHandler [WEAK]
|
||||
EXPORT EINT5_IRQHandler [WEAK]
|
||||
EXPORT GPA_IRQHandler [WEAK]
|
||||
EXPORT GPB_IRQHandler [WEAK]
|
||||
EXPORT GPC_IRQHandler [WEAK]
|
||||
EXPORT GPD_IRQHandler [WEAK]
|
||||
EXPORT GPE_IRQHandler [WEAK]
|
||||
EXPORT GPF_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT BRAKE0_IRQHandler [WEAK]
|
||||
EXPORT PWM0P0_IRQHandler [WEAK]
|
||||
EXPORT PWM0P1_IRQHandler [WEAK]
|
||||
EXPORT PWM0P2_IRQHandler [WEAK]
|
||||
EXPORT BRAKE1_IRQHandler [WEAK]
|
||||
EXPORT PWM1P0_IRQHandler [WEAK]
|
||||
EXPORT PWM1P1_IRQHandler [WEAK]
|
||||
EXPORT PWM1P2_IRQHandler [WEAK]
|
||||
EXPORT TMR0_IRQHandler [WEAK]
|
||||
EXPORT TMR1_IRQHandler [WEAK]
|
||||
EXPORT TMR2_IRQHandler [WEAK]
|
||||
EXPORT TMR3_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT PDMA_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT ADC00_IRQHandler [WEAK]
|
||||
EXPORT ADC01_IRQHandler [WEAK]
|
||||
EXPORT ACMP01_IRQHandler [WEAK]
|
||||
EXPORT ADC02_IRQHandler [WEAK]
|
||||
EXPORT ADC03_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT USBH_IRQHandler [WEAK]
|
||||
EXPORT USBOTG_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT SC0_IRQHandler [WEAK]
|
||||
EXPORT TK_IRQHandler [WEAK]
|
||||
|
||||
BOD_IRQHandler
|
||||
IRC_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
RAMPE_IRQHandler
|
||||
CLKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
WDT_IRQHandler
|
||||
WWDT_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
EINT2_IRQHandler
|
||||
EINT3_IRQHandler
|
||||
EINT4_IRQHandler
|
||||
EINT5_IRQHandler
|
||||
GPA_IRQHandler
|
||||
GPB_IRQHandler
|
||||
GPC_IRQHandler
|
||||
GPD_IRQHandler
|
||||
GPE_IRQHandler
|
||||
GPF_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
BRAKE0_IRQHandler
|
||||
PWM0P0_IRQHandler
|
||||
PWM0P1_IRQHandler
|
||||
PWM0P2_IRQHandler
|
||||
BRAKE1_IRQHandler
|
||||
PWM1P0_IRQHandler
|
||||
PWM1P1_IRQHandler
|
||||
PWM1P2_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
DAC_IRQHandler
|
||||
ADC00_IRQHandler
|
||||
ADC01_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
ADC02_IRQHandler
|
||||
ADC03_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USBD_IRQHandler
|
||||
USBH_IRQHandler
|
||||
USBOTG_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
SC0_IRQHandler
|
||||
TK_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
;/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/******************************************************************************
|
||||
* @file system_M451Series.c
|
||||
* @version V0.10
|
||||
* $Revision: 11 $
|
||||
* $Date: 15/09/02 10:02a $
|
||||
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "M451Series.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
|
||||
{
|
||||
#if 1
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
|
||||
if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
|
||||
//if(SystemCoreClock == 0)
|
||||
// __BKPT(0);
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param None
|
||||
* @return None
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* ToDo: add code to initialize the system
|
||||
do not use global variables because this function is called before
|
||||
reaching pre-main. RW section maybe overwritten afterwards. */
|
||||
|
||||
SYS_UnlockReg();
|
||||
/* One-time POR18 */
|
||||
if((SYS->PDID >> 12) == 0x945)
|
||||
{
|
||||
M32(GCR_BASE+0x14) |= BIT7;
|
||||
}
|
||||
/* Force to use INV type with HXT */
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
|
||||
SYS_LockReg();
|
||||
|
||||
|
||||
#ifdef EBI_INIT
|
||||
extern void SYS_Init();
|
||||
extern void EBI_Init();
|
||||
|
||||
SYS_UnlockReg();
|
||||
SYS_Init();
|
||||
EBI_Init();
|
||||
SYS_LockReg();
|
||||
#endif
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
|
||||
(3UL << 11 * 2)); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
}
|
||||
/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'roboticarm_controller'
|
||||
* Target: 'Target 1'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "M451Series.h"
|
||||
|
||||
#define RTE_Drivers_CLK /* Driver CLK */
|
||||
#define RTE_Drivers_GPIO /* Driver GPIO */
|
||||
#define RTE_Drivers_PWM /* Driver PWM */
|
||||
#define RTE_Drivers_SPI /* Driver SPI */
|
||||
#define RTE_Drivers_SYS /* Driver SYS */
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef __GLOBAL__
|
||||
#define __GLOBAL__
|
||||
|
||||
#include "stdio.h"
|
||||
#include "stdint.h"
|
||||
|
||||
extern short Axis1;
|
||||
extern short Axis2;
|
||||
extern short Axis3;
|
||||
extern short Axis4;
|
||||
extern short Axis5;
|
||||
extern short Axis6;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#include "M451Series.h"
|
||||
#include "global.h"
|
||||
|
||||
|
||||
void PWM0P0_IRQHandler(void)
|
||||
{
|
||||
static uint32_t lastStep = 0;
|
||||
|
||||
if(Axis1 != 0){
|
||||
PWM_EnableOutput(PWM0, PWM_CH_0_MASK);
|
||||
}
|
||||
else{
|
||||
PWM_DisableOutput(PWM0, PWM_CH_0_MASK);
|
||||
}
|
||||
if(Axis2 != 0){
|
||||
PWM_EnableOutput(PWM0, PWM_CH_1_MASK);
|
||||
}
|
||||
else{
|
||||
PWM_DisableOutput(PWM0, PWM_CH_1_MASK);
|
||||
}
|
||||
if(Axis3 != 0){
|
||||
PWM_EnableOutput(PWM0, PWM_CH_3_MASK);
|
||||
}
|
||||
else{
|
||||
PWM_DisableOutput(PWM0, PWM_CH_3_MASK);
|
||||
}
|
||||
if(Axis4 != 0){
|
||||
PWM_EnableOutput(PWM0, PWM_CH_4_MASK);
|
||||
}else{
|
||||
PWM_DisableOutput(PWM0, PWM_CH_4_MASK);
|
||||
}
|
||||
|
||||
// Clear channel 0 period interrupt flag
|
||||
PWM_ClearPeriodIntFlag(PWM0, 0);
|
||||
}
|
||||
|
||||
void PWM1P0_IRQHandler(void){
|
||||
if(Axis5 != 0){
|
||||
PWM_EnableOutput(PWM1, PWM_CH_0_MASK);
|
||||
}else{
|
||||
PWM_DisableOutput(PWM1, PWM_CH_0_MASK);
|
||||
}
|
||||
if(Axis6 != 0){
|
||||
PWM_EnableOutput(PWM1, PWM_CH_1_MASK);
|
||||
}else{
|
||||
PWM_DisableOutput(PWM1, PWM_CH_1_MASK);
|
||||
}
|
||||
PWM_ClearPeriodIntFlag(PWM1, 0);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
#include "M451Series.h"
|
||||
#include "spi_hal.h"
|
||||
#include "24l01.h"
|
||||
|
||||
|
||||
short Axis1 = 0;
|
||||
short Axis2 = 0;
|
||||
short Axis3 = 0;
|
||||
short Axis4 = 0;
|
||||
short Axis5 = 0;
|
||||
short Axis6 = 0;
|
||||
|
||||
void NRF24L01Init(){
|
||||
|
||||
|
||||
CLK_EnableModuleClock(SPI0_MODULE);
|
||||
|
||||
SYS_ResetModule(SPI0_RST);
|
||||
|
||||
/* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */
|
||||
/* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */
|
||||
CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, NULL);
|
||||
|
||||
/* Set PB multi-function pins for spi */
|
||||
SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB7MFP_Msk);
|
||||
SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 | SYS_GPB_MFPL_PB6MFP_SPI0_MISO0|SYS_GPB_MFPL_PB7MFP_SPI0_CLK);
|
||||
|
||||
SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk);
|
||||
SYS->GPB_MFPL |= (SYS_GPB_MFPH_PB13MFP_GPIO | SYS_GPB_MFPH_PB14MFP_GPIO|SYS_GPB_MFPH_PB15MFP_GPIO);
|
||||
|
||||
}
|
||||
|
||||
void PWMInit (){
|
||||
|
||||
CLK_EnableModuleClock(PWM0_MODULE);
|
||||
|
||||
SYS_ResetModule(PWM0_RST);
|
||||
|
||||
CLK_EnableModuleClock(PWM1_MODULE);
|
||||
|
||||
SYS_ResetModule(PWM1_RST);
|
||||
/* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */
|
||||
/* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */
|
||||
CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, NULL);
|
||||
CLK_SetModuleClock(PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, NULL);
|
||||
|
||||
/* Set PC multi-function pins for PWM0 Channel0~3 */
|
||||
SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SYS_GPC_MFPH_PC9MFP_Msk));
|
||||
SYS->GPC_MFPH |= SYS_GPC_MFPH_PC9MFP_PWM1_CH0;
|
||||
|
||||
SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SYS_GPC_MFPH_PC10MFP_Msk));
|
||||
SYS->GPC_MFPH |= SYS_GPC_MFPH_PC10MFP_PWM1_CH1;
|
||||
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC0MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_PWM0_CH0;
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC1MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC1MFP_PWM0_CH1;
|
||||
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC3MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC3MFP_PWM0_CH3;
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC4MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC4MFP_PWM0_CH4;
|
||||
|
||||
// PWM0 channel 0 frequency is 100Hz, duty 30%,
|
||||
PWM_ConfigOutputChannel(PWM0, 0, 20, 50);
|
||||
// PWM0 channel 2 frequency is 300Hz, duty 50%
|
||||
PWM_ConfigOutputChannel(PWM0, 1, 20, 50);
|
||||
// PWM0 channel 0 frequency is 100Hz, duty 30%,
|
||||
PWM_ConfigOutputChannel(PWM0, 3, 20, 30);
|
||||
// PWM0 channel 2 frequency is 300Hz, duty 50%
|
||||
PWM_ConfigOutputChannel(PWM0, 4, 20, 50);
|
||||
|
||||
// PWM0 channel 0 frequency is 100Hz, duty 30%,
|
||||
PWM_ConfigOutputChannel(PWM1, 0, 20, 50);
|
||||
// PWM0 channel 2 frequency is 300Hz, duty 50%
|
||||
PWM_ConfigOutputChannel(PWM1, 1, 20, 50);
|
||||
|
||||
// Enable output of PWM0 channel 0~3
|
||||
PWM_EnableOutput(PWM0, 0xF);
|
||||
// Enable PWM0 channel 0 period interrupt, use channel 0 to measure time.
|
||||
PWM_EnablePeriodInt(PWM0, 0, 0);
|
||||
NVIC_EnableIRQ(PWM0P0_IRQn);
|
||||
|
||||
// Start
|
||||
PWM_Start(PWM1, 0x3);
|
||||
PWM_EnablePeriodInt(PWM1, 0, 0);
|
||||
NVIC_EnableIRQ(PWM1P0_IRQn);
|
||||
// Start
|
||||
PWM_Start(PWM0, 0x1F);
|
||||
PWM_Start(PWM1, 0x1F);
|
||||
}
|
||||
|
||||
|
||||
void delay_1s(){
|
||||
for(volatile unsigned int x = 0;x < 100; x++){
|
||||
for(volatile unsigned int z = 0; z <100; z++){
|
||||
z = z;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int ParsePackage(unsigned char *dat){
|
||||
if( (dat[0] == 0xAA) && (dat[1] == 0xAF) && (dat[2] == 0x03) && (dat[3] == 0x1b)){
|
||||
Axis1 = (*(dat + 4)*256 + (*(dat + 5)));
|
||||
Axis2 = (*(dat + 6)*256 + (*(dat + 7)));
|
||||
Axis3 = (*(dat + 8)*256 + (*(dat + 9)));
|
||||
Axis4 = (*(dat + 10)*256 + (*(dat + 11)));
|
||||
Axis5 = (*(dat + 12)*256 + (*(dat + 13)));
|
||||
Axis6 = (*(dat + 14)*256 + (*(dat + 15)));
|
||||
}
|
||||
}
|
||||
int main(){
|
||||
unsigned char recv[32] = {0};
|
||||
GPIO_SetMode(PC,BIT9,GPIO_MODE_INPUT); //IRQ
|
||||
|
||||
Spi_init();
|
||||
RX_Mode();
|
||||
PWMInit ();
|
||||
while(1){
|
||||
if(NRF24L01_RxPacket(recv) == 0) {
|
||||
ParsePackage(recv);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>8</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>NULink\Nu_Link.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>Nu_Link</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M451_AP_256 -FS00 -FL040000 -FP0($$Device:M453VG6AE$Flash\M451_AP_256.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>Axis1</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>Axis2</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>Axis3</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>Axis4</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>Axis5</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>Axis6</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<SystemViewers>
|
||||
<Entry>
|
||||
<Name>System Viewer\SPI0</Name>
|
||||
<WinId>35905</WinId>
|
||||
</Entry>
|
||||
</SystemViewers>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\24l01.c</PathWithFileName>
|
||||
<FilenameWithoutPath>24l01.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\24l01.h</PathWithFileName>
|
||||
<FilenameWithoutPath>24l01.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\spi_hal.h</PathWithFileName>
|
||||
<FilenameWithoutPath>spi_hal.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\spi_hal.c</PathWithFileName>
|
||||
<FilenameWithoutPath>spi_hal.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\interrupt.c</PathWithFileName>
|
||||
<FilenameWithoutPath>interrupt.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\global.h</PathWithFileName>
|
||||
<FilenameWithoutPath>global.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,505 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>M453VG6AE</Device>
|
||||
<Vendor>Nuvoton</Vendor>
|
||||
<PackID>Nuvoton.NuMicro_DFP.1.2.0</PackID>
|
||||
<PackURL>http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M451_AP_256 -FS00 -FL040000 -FP0($$Device:M453VG6AE$Flash\M451_AP_256.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:M453VG6AE$Device\M451\Include\M451Series.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:M453VG6AE$SVD\Nuvoton\M451_v1.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>roboticarm_controller</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>1</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\Objects\roboticarm_controller.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>24l01.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\24l01.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>24l01.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\24l01.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>spi_hal.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\spi_hal.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>spi_hal.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\spi_hal.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>interrupt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\interrupt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>global.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\global.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.1.1" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="CLK" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="GPIO" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="PWM" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="SPI" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Driver" Csub="SYS" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device">
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="sourceC" name="Device\M451\Driver\retarget.c" version="3.01.001">
|
||||
<instance index="0">RTE\Device\M453VG6AE\retarget.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="sourceAsm" condition="Compiler ARM" name="Device\M451\Source\ARM\startup_M451Series.s" version="3.01.001">
|
||||
<instance index="0">RTE\Device\M453VG6AE\startup_M451Series.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="Device\M451\Source\system_M451Series.c" version="3.01.001">
|
||||
<instance index="0">RTE\Device\M453VG6AE\system_M451Series.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Nuvoton" Cversion="3.01.001" condition="M4NuMicro M451 Device"/>
|
||||
<package name="NuMicro_DFP" schemaVersion="1.2" url="http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack" vendor="Nuvoton" version="1.2.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="Target 1"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
#include "M451Series.h"
|
||||
#include "spi_hal.h"
|
||||
|
||||
void Spi_init()
|
||||
{
|
||||
/* Set PB multi-function pins for spi */
|
||||
SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB7MFP_Msk);
|
||||
SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 | SYS_GPB_MFPL_PB6MFP_SPI0_MISO0|SYS_GPB_MFPL_PB7MFP_SPI0_CLK);
|
||||
|
||||
SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk);
|
||||
SYS->GPB_MFPL |= (SYS_GPB_MFPH_PB13MFP_GPIO | SYS_GPB_MFPH_PB14MFP_GPIO|SYS_GPB_MFPH_PB15MFP_GPIO);
|
||||
|
||||
//SYS->GPC_MFP|=((0x01<<0)|(0x01<<1)|(0x01<<2)|(0x01<<3));
|
||||
GPIO_SetMode(PB,BIT14,GPIO_MODE_OUTPUT); // CSN
|
||||
GPIO_SetMode(PB,BIT13,GPIO_MODE_OUTPUT); // CE
|
||||
GPIO_SetMode(PB,BIT15,GPIO_MODE_INPUT); //IRQ
|
||||
|
||||
PB14 = 1;
|
||||
PB13= 0;
|
||||
|
||||
CLK_EnableModuleClock(SPI0_MODULE);
|
||||
|
||||
SYS_ResetModule(SPI0_RST);
|
||||
|
||||
/* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */
|
||||
/* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */
|
||||
CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, NULL);
|
||||
|
||||
SPI_Open(SPI0,SPI_MASTER,SPI_MODE_0,8,40000);
|
||||
|
||||
SPI_DisableAutoSS(SPI0);
|
||||
}
|
||||
|
||||
void delayAny(){
|
||||
for(int x = 0;x < 15;x++){
|
||||
x = x;;
|
||||
}
|
||||
}
|
||||
void spi_enable()
|
||||
{
|
||||
PB14= 0;
|
||||
delayAny();
|
||||
|
||||
//SPI_SET_SS_LOW(SPI0);
|
||||
}
|
||||
void spi_disable()
|
||||
{
|
||||
delayAny();
|
||||
|
||||
PB14 = 1;
|
||||
//SPI_SET_SS_HIGH(SPI0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
*/
|
||||
uchar spi_send(unsigned char data)
|
||||
{
|
||||
SPI_WRITE_TX(SPI0,data);
|
||||
while(SPI_IS_BUSY(SPI0) == 1) ;
|
||||
return SPI_READ_RX(SPI0);
|
||||
}
|
||||
/*
|
||||
|
||||
*/
|
||||
uchar spi_read()
|
||||
{
|
||||
uchar ret;
|
||||
SPI_WRITE_TX(SPI0, 0x0);
|
||||
while(SPI_IS_BUSY(SPI0) == 1) ;
|
||||
ret= SPI_READ_RX(SPI0);
|
||||
//SPI0->CNTRL.IF=1;
|
||||
return ret;
|
||||
}
|
||||
|
||||
uchar nrf_read(uchar adress)
|
||||
{
|
||||
uchar ret;
|
||||
spi_enable();
|
||||
spi_send(adress);
|
||||
|
||||
ret= spi_read();
|
||||
spi_disable();
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
uchar nrf_wf(unsigned char dat)
|
||||
{
|
||||
uchar ret;
|
||||
spi_enable();
|
||||
spi_send(dat);
|
||||
spi_disable();
|
||||
return ret;
|
||||
}
|
||||
|
||||
uchar nrf_write(uchar adress,uchar data)
|
||||
{
|
||||
uchar ret;
|
||||
spi_enable();
|
||||
spi_send(adress);
|
||||
spi_send(data);
|
||||
spi_disable();
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*****************SPI??TXFIFO?????**********************************/
|
||||
uchar NRFWriteTxDate(uchar RegAddr,uchar *TxDate,uchar DateLen)
|
||||
{
|
||||
uchar BackDate,i;
|
||||
BackDate=spi_send(RegAddr);
|
||||
for(i=0;i<DateLen;i++)
|
||||
{
|
||||
spi_send(*TxDate++);
|
||||
}
|
||||
return(BackDate);
|
||||
}
|
||||
|
||||
|
||||
//在指定位置写指定长度的数据
|
||||
//reg:寄存器(位置)
|
||||
//*pBuf:数据指针
|
||||
//len:数据长度
|
||||
//返回值,此次读到的状态寄存器值
|
||||
uchar nrf_writebuf(uchar reg, uchar *pBuf, uchar len)
|
||||
{
|
||||
uchar status,u8_ctr;
|
||||
spi_enable();
|
||||
status = spi_send(reg);//发送寄存器值(位置),并读取状态值
|
||||
for(u8_ctr=0; u8_ctr<len; u8_ctr++)
|
||||
spi_send(*pBuf++); //写入数据
|
||||
spi_disable();
|
||||
return status; //返回读到的状态值
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#ifndef __SPI_HAL__
|
||||
#define __SPI_HAL__
|
||||
|
||||
|
||||
#define uchar unsigned char
|
||||
|
||||
void Spi_init(void);
|
||||
void spi_enable(void);
|
||||
uchar spi_send(unsigned char data);
|
||||
uchar spi_read(void);
|
||||
uchar nrf_writebuf(uchar reg, uchar *pBuf, uchar len);
|
||||
uchar nrf_write(uchar adress,uchar data);
|
||||
uchar nrf_read(uchar adress);
|
||||
uchar nrf_writebuf(uchar reg, uchar *pBuf, uchar len);
|
||||
void spi_disable(void);
|
||||
uchar nrf_wf(unsigned char dat);
|
||||
|
||||
#endif
|
||||
|
||||
Binary file not shown.
|
|
@ -63,6 +63,7 @@ Section Cross References
|
|||
main.o(i.main) refers to main.o(i._Z17EADC_FunctionTestv) for EADC_FunctionTest()
|
||||
main.o(i.main) refers to system_m451series.o(.data) for SystemCoreClock
|
||||
main.o(.ARM.exidx) refers to main.o(i._Z13SYS_UnlockRegv) for i._Z13SYS_UnlockRegv
|
||||
main.o(.ARM.exidx) refers to main.o(i._Z12NRF24L01Initv) for i._Z12NRF24L01Initv
|
||||
main.o(.ARM.exidx) refers to main.o(i._Z7PWMInitv) for i._Z7PWMInitv
|
||||
main.o(.ARM.exidx) refers to main.o(i._Z7I2CInitv) for i._Z7I2CInitv
|
||||
main.o(.ARM.exidx) refers to main.o(i._Z8SYS_Initv) for i._Z8SYS_Initv
|
||||
|
|
@ -303,6 +304,7 @@ Removing Unused input sections from the image.
|
|||
|
||||
Removing main.o(.rev16_text), (4 bytes).
|
||||
Removing main.o(.revsh_text), (4 bytes).
|
||||
Removing main.o(i._Z12NRF24L01Initv), (136 bytes).
|
||||
Removing main.o(i._Z16ADC00_IRQHandlerv), (20 bytes).
|
||||
Removing main.o(.ARM.exidx), (8 bytes).
|
||||
Removing main.o(.ARM.exidx), (8 bytes).
|
||||
|
|
@ -313,6 +315,7 @@ Removing Unused input sections from the image.
|
|||
Removing main.o(.ARM.exidx), (8 bytes).
|
||||
Removing main.o(.ARM.exidx), (8 bytes).
|
||||
Removing main.o(.ARM.exidx), (8 bytes).
|
||||
Removing main.o(.ARM.exidx), (8 bytes).
|
||||
Removing ssd1306.o(.rev16_text), (4 bytes).
|
||||
Removing ssd1306.o(.revsh_text), (4 bytes).
|
||||
Removing ssd1306.o(i.OLED_SingleRead), (220 bytes).
|
||||
|
|
@ -466,7 +469,7 @@ Removing Unused input sections from the image.
|
|||
Removing i2c.o(i.I2C_SetSlaveAddrMask), (46 bytes).
|
||||
Removing i2c.o(i.I2C_Trigger), (44 bytes).
|
||||
|
||||
164 unused section(s) (total 4484 bytes) removed from the image.
|
||||
166 unused section(s) (total 4628 bytes) removed from the image.
|
||||
|
||||
==============================================================================
|
||||
|
||||
|
|
@ -1010,164 +1013,164 @@ Memory Map of the image
|
|||
|
||||
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
|
||||
|
||||
0x00000000 0x00000000 0x00000140 Data RO 1323 RESET startup_m451series.o
|
||||
0x00000140 0x00000140 0x00000008 Code RO 1624 * !!!main c_w.l(__main.o)
|
||||
0x00000148 0x00000148 0x00000034 Code RO 1792 !!!scatter c_w.l(__scatter.o)
|
||||
0x0000017c 0x0000017c 0x0000005a Code RO 1790 !!dczerorl2 c_w.l(__dczerorl2.o)
|
||||
0x00000000 0x00000000 0x00000140 Data RO 1330 RESET startup_m451series.o
|
||||
0x00000140 0x00000140 0x00000008 Code RO 1631 * !!!main c_w.l(__main.o)
|
||||
0x00000148 0x00000148 0x00000034 Code RO 1799 !!!scatter c_w.l(__scatter.o)
|
||||
0x0000017c 0x0000017c 0x0000005a Code RO 1797 !!dczerorl2 c_w.l(__dczerorl2.o)
|
||||
0x000001d6 0x000001d6 0x00000002 PAD
|
||||
0x000001d8 0x000001d8 0x0000001c Code RO 1794 !!handler_zi c_w.l(__scatter_zi.o)
|
||||
0x000001f4 0x000001f4 0x00000000 Code RO 1617 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o)
|
||||
0x000001f4 0x000001f4 0x00000006 Code RO 1616 .ARM.Collect$$_printf_percent$$00000009 c_w.l(_printf_d.o)
|
||||
0x000001fa 0x000001fa 0x00000006 Code RO 1615 .ARM.Collect$$_printf_percent$$0000000C c_w.l(_printf_x.o)
|
||||
0x00000200 0x00000200 0x00000004 Code RO 1635 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o)
|
||||
0x00000204 0x00000204 0x00000002 Code RO 1662 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o)
|
||||
0x00000206 0x00000206 0x00000004 Code RO 1668 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1671 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1674 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1676 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1678 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1681 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1683 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1685 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1687 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1689 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1691 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1693 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1695 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1697 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1699 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1701 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1705 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1707 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1709 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1711 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000002 Code RO 1712 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o)
|
||||
0x0000020c 0x0000020c 0x00000002 Code RO 1732 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1745 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1747 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1750 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1753 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1755 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1758 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000002 Code RO 1759 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o)
|
||||
0x00000210 0x00000210 0x00000000 Code RO 1626 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o)
|
||||
0x00000210 0x00000210 0x00000000 Code RO 1637 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o)
|
||||
0x00000210 0x00000210 0x00000006 Code RO 1649 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o)
|
||||
0x00000216 0x00000216 0x00000000 Code RO 1639 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o)
|
||||
0x00000216 0x00000216 0x00000004 Code RO 1640 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o)
|
||||
0x0000021a 0x0000021a 0x00000000 Code RO 1642 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o)
|
||||
0x0000021a 0x0000021a 0x00000008 Code RO 1643 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o)
|
||||
0x00000222 0x00000222 0x00000002 Code RO 1666 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o)
|
||||
0x00000224 0x00000224 0x00000000 Code RO 1714 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o)
|
||||
0x00000224 0x00000224 0x00000004 Code RO 1715 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o)
|
||||
0x00000228 0x00000228 0x00000006 Code RO 1716 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o)
|
||||
0x000001d8 0x000001d8 0x0000001c Code RO 1801 !!handler_zi c_w.l(__scatter_zi.o)
|
||||
0x000001f4 0x000001f4 0x00000000 Code RO 1624 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o)
|
||||
0x000001f4 0x000001f4 0x00000006 Code RO 1623 .ARM.Collect$$_printf_percent$$00000009 c_w.l(_printf_d.o)
|
||||
0x000001fa 0x000001fa 0x00000006 Code RO 1622 .ARM.Collect$$_printf_percent$$0000000C c_w.l(_printf_x.o)
|
||||
0x00000200 0x00000200 0x00000004 Code RO 1642 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o)
|
||||
0x00000204 0x00000204 0x00000002 Code RO 1669 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o)
|
||||
0x00000206 0x00000206 0x00000004 Code RO 1675 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1678 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1681 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1683 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1685 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1688 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1690 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1692 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1694 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1696 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1698 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1700 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1702 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1704 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1706 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1708 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1712 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1714 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1716 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000000 Code RO 1718 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o)
|
||||
0x0000020a 0x0000020a 0x00000002 Code RO 1719 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o)
|
||||
0x0000020c 0x0000020c 0x00000002 Code RO 1739 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1752 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1754 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1757 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1760 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1762 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000000 Code RO 1765 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o)
|
||||
0x0000020e 0x0000020e 0x00000002 Code RO 1766 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o)
|
||||
0x00000210 0x00000210 0x00000000 Code RO 1633 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o)
|
||||
0x00000210 0x00000210 0x00000000 Code RO 1644 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o)
|
||||
0x00000210 0x00000210 0x00000006 Code RO 1656 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o)
|
||||
0x00000216 0x00000216 0x00000000 Code RO 1646 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o)
|
||||
0x00000216 0x00000216 0x00000004 Code RO 1647 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o)
|
||||
0x0000021a 0x0000021a 0x00000000 Code RO 1649 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o)
|
||||
0x0000021a 0x0000021a 0x00000008 Code RO 1650 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o)
|
||||
0x00000222 0x00000222 0x00000002 Code RO 1673 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o)
|
||||
0x00000224 0x00000224 0x00000000 Code RO 1721 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o)
|
||||
0x00000224 0x00000224 0x00000004 Code RO 1722 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o)
|
||||
0x00000228 0x00000228 0x00000006 Code RO 1723 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o)
|
||||
0x0000022e 0x0000022e 0x00000002 PAD
|
||||
0x00000230 0x00000230 0x0000001c Code RO 1001 .emb_text retarget.o
|
||||
0x0000024c 0x0000024c 0x00000074 Code RO 1324 * .text startup_m451series.o
|
||||
0x000002c0 0x000002c0 0x00000018 Code RO 1566 .text c_w.l(noretval__2printf.o)
|
||||
0x000002d8 0x000002d8 0x00000028 Code RO 1568 .text c_w.l(noretval__2sprintf.o)
|
||||
0x00000300 0x00000300 0x00000078 Code RO 1572 .text c_w.l(_printf_dec.o)
|
||||
0x00000378 0x00000378 0x00000058 Code RO 1577 .text c_w.l(_printf_hex_int.o)
|
||||
0x000003d0 0x000003d0 0x0000010e Code RO 1603 .text c_w.l(__printf_wp.o)
|
||||
0x000004de 0x000004de 0x0000003e Code RO 1618 .text c_w.l(strlen.o)
|
||||
0x0000051c 0x0000051c 0x0000004e Code RO 1620 .text c_w.l(rt_memclr_w.o)
|
||||
0x0000056a 0x0000056a 0x00000006 Code RO 1622 .text c_w.l(heapauxi.o)
|
||||
0x00000570 0x00000570 0x000000b2 Code RO 1627 .text c_w.l(_printf_intcommon.o)
|
||||
0x00000230 0x00000230 0x0000001c Code RO 1008 .emb_text retarget.o
|
||||
0x0000024c 0x0000024c 0x00000074 Code RO 1331 * .text startup_m451series.o
|
||||
0x000002c0 0x000002c0 0x00000018 Code RO 1573 .text c_w.l(noretval__2printf.o)
|
||||
0x000002d8 0x000002d8 0x00000028 Code RO 1575 .text c_w.l(noretval__2sprintf.o)
|
||||
0x00000300 0x00000300 0x00000078 Code RO 1579 .text c_w.l(_printf_dec.o)
|
||||
0x00000378 0x00000378 0x00000058 Code RO 1584 .text c_w.l(_printf_hex_int.o)
|
||||
0x000003d0 0x000003d0 0x0000010e Code RO 1610 .text c_w.l(__printf_wp.o)
|
||||
0x000004de 0x000004de 0x0000003e Code RO 1625 .text c_w.l(strlen.o)
|
||||
0x0000051c 0x0000051c 0x0000004e Code RO 1627 .text c_w.l(rt_memclr_w.o)
|
||||
0x0000056a 0x0000056a 0x00000006 Code RO 1629 .text c_w.l(heapauxi.o)
|
||||
0x00000570 0x00000570 0x000000b2 Code RO 1634 .text c_w.l(_printf_intcommon.o)
|
||||
0x00000622 0x00000622 0x00000002 PAD
|
||||
0x00000624 0x00000624 0x00000030 Code RO 1629 .text c_w.l(_printf_char_common.o)
|
||||
0x00000654 0x00000654 0x0000000a Code RO 1631 .text c_w.l(_sputc.o)
|
||||
0x00000624 0x00000624 0x00000030 Code RO 1636 .text c_w.l(_printf_char_common.o)
|
||||
0x00000654 0x00000654 0x0000000a Code RO 1638 .text c_w.l(_sputc.o)
|
||||
0x0000065e 0x0000065e 0x00000002 PAD
|
||||
0x00000660 0x00000660 0x00000024 Code RO 1633 .text c_w.l(_printf_char_file.o)
|
||||
0x00000684 0x00000684 0x0000004a Code RO 1653 .text c_w.l(sys_stackheap_outer.o)
|
||||
0x000006ce 0x000006ce 0x00000012 Code RO 1655 .text c_w.l(exit.o)
|
||||
0x000006e0 0x000006e0 0x00000008 Code RO 1663 .text c_w.l(libspace.o)
|
||||
0x000006e8 0x000006e8 0x0000000c Code RO 1724 .text c_w.l(sys_exit.o)
|
||||
0x000006f4 0x000006f4 0x00000002 Code RO 1735 .text c_w.l(use_no_semi.o)
|
||||
0x000006f6 0x000006f6 0x00000000 Code RO 1737 .text c_w.l(indicate_semi.o)
|
||||
0x00000660 0x00000660 0x00000024 Code RO 1640 .text c_w.l(_printf_char_file.o)
|
||||
0x00000684 0x00000684 0x0000004a Code RO 1660 .text c_w.l(sys_stackheap_outer.o)
|
||||
0x000006ce 0x000006ce 0x00000012 Code RO 1662 .text c_w.l(exit.o)
|
||||
0x000006e0 0x000006e0 0x00000008 Code RO 1670 .text c_w.l(libspace.o)
|
||||
0x000006e8 0x000006e8 0x0000000c Code RO 1731 .text c_w.l(sys_exit.o)
|
||||
0x000006f4 0x000006f4 0x00000002 Code RO 1742 .text c_w.l(use_no_semi.o)
|
||||
0x000006f6 0x000006f6 0x00000000 Code RO 1744 .text c_w.l(indicate_semi.o)
|
||||
0x000006f6 0x000006f6 0x00000002 PAD
|
||||
0x000006f8 0x000006f8 0x00000018 Code RO 419 i.CLK_DisablePLL clk.o
|
||||
0x00000710 0x00000710 0x0000002c Code RO 423 i.CLK_EnableModuleClock clk.o
|
||||
0x0000073c 0x0000073c 0x00000178 Code RO 424 i.CLK_EnablePLL clk.o
|
||||
0x000008b4 0x000008b4 0x00000014 Code RO 426 i.CLK_EnableXtalRC clk.o
|
||||
0x000008c8 0x000008c8 0x00000028 Code RO 431 i.CLK_GetPCLK0Freq clk.o
|
||||
0x000008f0 0x000008f0 0x00000028 Code RO 432 i.CLK_GetPCLK1Freq clk.o
|
||||
0x00000918 0x00000918 0x00000064 Code RO 433 i.CLK_GetPLLClockFreq clk.o
|
||||
0x0000097c 0x0000097c 0x00000064 Code RO 577 i.CLK_GetPLLClockFreq pwm.o
|
||||
0x000009e0 0x000009e0 0x00000064 Code RO 1165 i.CLK_GetPLLClockFreq uart.o
|
||||
0x00000a44 0x00000a44 0x00000064 Code RO 1283 i.CLK_GetPLLClockFreq system_m451series.o
|
||||
0x00000aa8 0x00000aa8 0x000000ac Code RO 436 i.CLK_SetCoreClock clk.o
|
||||
0x00000b54 0x00000b54 0x0000007c Code RO 437 i.CLK_SetHCLK clk.o
|
||||
0x00000bd0 0x00000bd0 0x00000054 Code RO 438 i.CLK_SetModuleClock clk.o
|
||||
0x00000c24 0x00000c24 0x00000028 Code RO 440 i.CLK_WaitClockReady clk.o
|
||||
0x00000c4c 0x00000c4c 0x00000030 Code RO 1331 i.EADC_ConfigSampleModule eadc.o
|
||||
0x00000c7c 0x00000c7c 0x00000014 Code RO 1332 i.EADC_Open eadc.o
|
||||
0x00000c90 0x00000c90 0x00000014 Code RO 1334 i.EADC_SetInternalSampleTime eadc.o
|
||||
0x00000ca4 0x00000ca4 0x0000002c Code RO 1003 i.Hard_Fault_Handler retarget.o
|
||||
0x00000cd0 0x00000cd0 0x00000028 Code RO 1388 i.I2C_GetBusClockFreq i2c.o
|
||||
0x00000cf8 0x00000cf8 0x0000004c Code RO 1392 i.I2C_Open i2c.o
|
||||
0x00000d44 0x00000d44 0x00000038 Code RO 1405 i.I2C_SetSlaveAddr i2c.o
|
||||
0x00000d7c 0x00000d7c 0x000000ac Code RO 187 i.Init_LCD ssd1306.o
|
||||
0x00000e28 0x00000e28 0x00000098 Code RO 189 i.OLED_SingleWrite ssd1306.o
|
||||
0x00000ec0 0x00000ec0 0x00000050 Code RO 374 i.PWM0P0_IRQHandler interrupt.o
|
||||
0x00000f10 0x00000f10 0x0000000c Code RO 585 i.PWM_ClearPeriodIntFlag pwm.o
|
||||
0x00000f1c 0x00000f1c 0x00000170 Code RO 589 i.PWM_ConfigOutputChannel pwm.o
|
||||
0x0000108c 0x0000108c 0x0000000c Code RO 603 i.PWM_DisableOutput pwm.o
|
||||
0x00001098 0x00001098 0x00000032 Code RO 618 i.PWM_EnableDeadZone pwm.o
|
||||
0x000010ca 0x000010ca 0x0000000c Code RO 623 i.PWM_EnableOutput pwm.o
|
||||
0x000010d6 0x000010d6 0x00000014 Code RO 625 i.PWM_EnablePeriodInt pwm.o
|
||||
0x000010ea 0x000010ea 0x00000008 Code RO 643 i.PWM_Start pwm.o
|
||||
0x000010f2 0x000010f2 0x00000030 Code RO 1100 i.SYS_ResetModule sys.o
|
||||
0x00001122 0x00001122 0x0000000c Code RO 1005 i.SendChar retarget.o
|
||||
0x000006f8 0x000006f8 0x00000018 Code RO 426 i.CLK_DisablePLL clk.o
|
||||
0x00000710 0x00000710 0x0000002c Code RO 430 i.CLK_EnableModuleClock clk.o
|
||||
0x0000073c 0x0000073c 0x00000178 Code RO 431 i.CLK_EnablePLL clk.o
|
||||
0x000008b4 0x000008b4 0x00000014 Code RO 433 i.CLK_EnableXtalRC clk.o
|
||||
0x000008c8 0x000008c8 0x00000028 Code RO 438 i.CLK_GetPCLK0Freq clk.o
|
||||
0x000008f0 0x000008f0 0x00000028 Code RO 439 i.CLK_GetPCLK1Freq clk.o
|
||||
0x00000918 0x00000918 0x00000064 Code RO 440 i.CLK_GetPLLClockFreq clk.o
|
||||
0x0000097c 0x0000097c 0x00000064 Code RO 584 i.CLK_GetPLLClockFreq pwm.o
|
||||
0x000009e0 0x000009e0 0x00000064 Code RO 1172 i.CLK_GetPLLClockFreq uart.o
|
||||
0x00000a44 0x00000a44 0x00000064 Code RO 1290 i.CLK_GetPLLClockFreq system_m451series.o
|
||||
0x00000aa8 0x00000aa8 0x000000ac Code RO 443 i.CLK_SetCoreClock clk.o
|
||||
0x00000b54 0x00000b54 0x0000007c Code RO 444 i.CLK_SetHCLK clk.o
|
||||
0x00000bd0 0x00000bd0 0x00000054 Code RO 445 i.CLK_SetModuleClock clk.o
|
||||
0x00000c24 0x00000c24 0x00000028 Code RO 447 i.CLK_WaitClockReady clk.o
|
||||
0x00000c4c 0x00000c4c 0x00000030 Code RO 1338 i.EADC_ConfigSampleModule eadc.o
|
||||
0x00000c7c 0x00000c7c 0x00000014 Code RO 1339 i.EADC_Open eadc.o
|
||||
0x00000c90 0x00000c90 0x00000014 Code RO 1341 i.EADC_SetInternalSampleTime eadc.o
|
||||
0x00000ca4 0x00000ca4 0x0000002c Code RO 1010 i.Hard_Fault_Handler retarget.o
|
||||
0x00000cd0 0x00000cd0 0x00000028 Code RO 1395 i.I2C_GetBusClockFreq i2c.o
|
||||
0x00000cf8 0x00000cf8 0x0000004c Code RO 1399 i.I2C_Open i2c.o
|
||||
0x00000d44 0x00000d44 0x00000038 Code RO 1412 i.I2C_SetSlaveAddr i2c.o
|
||||
0x00000d7c 0x00000d7c 0x000000ac Code RO 194 i.Init_LCD ssd1306.o
|
||||
0x00000e28 0x00000e28 0x00000098 Code RO 196 i.OLED_SingleWrite ssd1306.o
|
||||
0x00000ec0 0x00000ec0 0x00000050 Code RO 381 i.PWM0P0_IRQHandler interrupt.o
|
||||
0x00000f10 0x00000f10 0x0000000c Code RO 592 i.PWM_ClearPeriodIntFlag pwm.o
|
||||
0x00000f1c 0x00000f1c 0x00000170 Code RO 596 i.PWM_ConfigOutputChannel pwm.o
|
||||
0x0000108c 0x0000108c 0x0000000c Code RO 610 i.PWM_DisableOutput pwm.o
|
||||
0x00001098 0x00001098 0x00000032 Code RO 625 i.PWM_EnableDeadZone pwm.o
|
||||
0x000010ca 0x000010ca 0x0000000c Code RO 630 i.PWM_EnableOutput pwm.o
|
||||
0x000010d6 0x000010d6 0x00000014 Code RO 632 i.PWM_EnablePeriodInt pwm.o
|
||||
0x000010ea 0x000010ea 0x00000008 Code RO 650 i.PWM_Start pwm.o
|
||||
0x000010f2 0x000010f2 0x00000030 Code RO 1107 i.SYS_ResetModule sys.o
|
||||
0x00001122 0x00001122 0x0000000c Code RO 1012 i.SendChar retarget.o
|
||||
0x0000112e 0x0000112e 0x00000002 PAD
|
||||
0x00001130 0x00001130 0x00000030 Code RO 1006 i.SendChar_ToUART retarget.o
|
||||
0x00001160 0x00001160 0x00000064 Code RO 1284 i.SystemCoreClockUpdate system_m451series.o
|
||||
0x000011c4 0x000011c4 0x00000074 Code RO 1285 i.SystemInit system_m451series.o
|
||||
0x00001238 0x00001238 0x00000094 Code RO 1174 i.UART_Open uart.o
|
||||
0x00001130 0x00001130 0x00000030 Code RO 1013 i.SendChar_ToUART retarget.o
|
||||
0x00001160 0x00001160 0x00000064 Code RO 1291 i.SystemCoreClockUpdate system_m451series.o
|
||||
0x000011c4 0x000011c4 0x00000074 Code RO 1292 i.SystemInit system_m451series.o
|
||||
0x00001238 0x00001238 0x00000094 Code RO 1181 i.UART_Open uart.o
|
||||
0x000012cc 0x000012cc 0x0000001c Code RO 3 i._Z10UART0_Initv main.o
|
||||
0x000012e8 0x000012e8 0x0000000c Code RO 4 i._Z11SYS_LockRegv main.o
|
||||
0x000012f4 0x000012f4 0x00000028 Code RO 5 i._Z13SYS_UnlockRegv main.o
|
||||
0x0000131c 0x0000131c 0x00000210 Code RO 7 i._Z17EADC_FunctionTestv main.o
|
||||
0x0000152c 0x0000152c 0x00000080 Code RO 8 i._Z7I2CInitv main.o
|
||||
0x000015ac 0x000015ac 0x0000010c Code RO 9 i._Z7PWMInitv main.o
|
||||
0x000016b8 0x000016b8 0x000000a8 Code RO 10 i._Z8SYS_Initv main.o
|
||||
0x00001760 0x00001760 0x0000000e Code RO 1605 i._is_digit c_w.l(__printf_wp.o)
|
||||
0x0000176e 0x0000176e 0x0000002a Code RO 190 i.clear_LCD ssd1306.o
|
||||
0x00001798 0x00001798 0x00000008 Code RO 1008 i.ferror retarget.o
|
||||
0x000017a0 0x000017a0 0x00000010 Code RO 1010 i.fputc retarget.o
|
||||
0x000017b0 0x000017b0 0x00000048 Code RO 11 i.main main.o
|
||||
0x000017f8 0x000017f8 0x0000000e Code RO 192 i.oledWriteCommand ssd1306.o
|
||||
0x00001806 0x00001806 0x0000000e Code RO 193 i.oledWriteData ssd1306.o
|
||||
0x00001814 0x00001814 0x00000024 Code RO 194 i.oled_address ssd1306.o
|
||||
0x00001838 0x00001838 0x00000050 Code RO 195 i.print_C ssd1306.o
|
||||
0x00001888 0x00001888 0x00000024 Code RO 196 i.print_Line ssd1306.o
|
||||
0x000018ac 0x000018ac 0x000000a8 Code RO 1012 i.stackDump retarget.o
|
||||
0x00001954 0x00001954 0x0000000a Code RO 1722 x$fpl$fpinit fz_wm.l(fpinit.o)
|
||||
0x000012f4 0x000012f4 0x00000028 Code RO 6 i._Z13SYS_UnlockRegv main.o
|
||||
0x0000131c 0x0000131c 0x00000210 Code RO 8 i._Z17EADC_FunctionTestv main.o
|
||||
0x0000152c 0x0000152c 0x00000080 Code RO 9 i._Z7I2CInitv main.o
|
||||
0x000015ac 0x000015ac 0x0000010c Code RO 10 i._Z7PWMInitv main.o
|
||||
0x000016b8 0x000016b8 0x000000a8 Code RO 11 i._Z8SYS_Initv main.o
|
||||
0x00001760 0x00001760 0x0000000e Code RO 1612 i._is_digit c_w.l(__printf_wp.o)
|
||||
0x0000176e 0x0000176e 0x0000002a Code RO 197 i.clear_LCD ssd1306.o
|
||||
0x00001798 0x00001798 0x00000008 Code RO 1015 i.ferror retarget.o
|
||||
0x000017a0 0x000017a0 0x00000010 Code RO 1017 i.fputc retarget.o
|
||||
0x000017b0 0x000017b0 0x00000048 Code RO 12 i.main main.o
|
||||
0x000017f8 0x000017f8 0x0000000e Code RO 199 i.oledWriteCommand ssd1306.o
|
||||
0x00001806 0x00001806 0x0000000e Code RO 200 i.oledWriteData ssd1306.o
|
||||
0x00001814 0x00001814 0x00000024 Code RO 201 i.oled_address ssd1306.o
|
||||
0x00001838 0x00001838 0x00000050 Code RO 202 i.print_C ssd1306.o
|
||||
0x00001888 0x00001888 0x00000024 Code RO 203 i.print_Line ssd1306.o
|
||||
0x000018ac 0x000018ac 0x000000a8 Code RO 1019 i.stackDump retarget.o
|
||||
0x00001954 0x00001954 0x0000000a Code RO 1729 x$fpl$fpinit fz_wm.l(fpinit.o)
|
||||
0x0000195e 0x0000195e 0x00000002 PAD
|
||||
0x00001960 0x00001960 0x00000030 Data RO 1182 .constdata uart.o
|
||||
0x00001990 0x00001990 0x00000028 Data RO 1578 .constdata c_w.l(_printf_hex_int.o)
|
||||
0x000019b8 0x000019b8 0x000000f6 Data RO 21 .conststring main.o
|
||||
0x00001960 0x00001960 0x00000030 Data RO 1189 .constdata uart.o
|
||||
0x00001990 0x00001990 0x00000028 Data RO 1585 .constdata c_w.l(_printf_hex_int.o)
|
||||
0x000019b8 0x000019b8 0x000000f6 Data RO 23 .conststring main.o
|
||||
0x00001aae 0x00001aae 0x00000002 PAD
|
||||
0x00001ab0 0x00001ab0 0x00000020 Data RO 1788 Region$$Table anon$$obj.o
|
||||
0x00001ab0 0x00001ab0 0x00000020 Data RO 1795 Region$$Table anon$$obj.o
|
||||
|
||||
|
||||
Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x00001ad0, Size: 0x00001060, Max: 0xffffffff, ABSOLUTE, COMPRESSED[0x00000958])
|
||||
|
||||
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
|
||||
|
||||
0x20000000 COMPRESSED 0x0000000c Data RW 22 .data main.o
|
||||
0x2000000c COMPRESSED 0x00001018 Data RW 197 .data ssd1306.o
|
||||
0x20001024 COMPRESSED 0x00000008 Data RW 375 .data interrupt.o
|
||||
0x2000102c COMPRESSED 0x00000008 Data RW 1013 .data retarget.o
|
||||
0x20001034 COMPRESSED 0x0000002c Data RW 1286 .data system_m451series.o
|
||||
0x20000000 COMPRESSED 0x0000000c Data RW 24 .data main.o
|
||||
0x2000000c COMPRESSED 0x00001018 Data RW 204 .data ssd1306.o
|
||||
0x20001024 COMPRESSED 0x00000008 Data RW 382 .data interrupt.o
|
||||
0x2000102c COMPRESSED 0x00000008 Data RW 1020 .data retarget.o
|
||||
0x20001034 COMPRESSED 0x0000002c Data RW 1293 .data system_m451series.o
|
||||
|
||||
|
||||
Execution Region ER_ZI (Exec base: 0x20001060, Load base: 0x00002428, Size: 0x00000460, Max: 0xffffffff, ABSOLUTE)
|
||||
|
||||
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
|
||||
|
||||
0x20001060 - 0x00000060 Zero RW 1664 .bss c_w.l(libspace.o)
|
||||
0x200010c0 - 0x00000000 Zero RW 1322 HEAP startup_m451series.o
|
||||
0x200010c0 - 0x00000400 Zero RW 1321 STACK startup_m451series.o
|
||||
0x20001060 - 0x00000060 Zero RW 1671 .bss c_w.l(libspace.o)
|
||||
0x200010c0 - 0x00000000 Zero RW 1329 HEAP startup_m451series.o
|
||||
0x200010c0 - 0x00000400 Zero RW 1328 STACK startup_m451series.o
|
||||
|
||||
|
||||
==============================================================================
|
||||
|
|
@ -1181,7 +1184,7 @@ Image component sizes
|
|||
88 4 0 0 0 2063 eadc.o
|
||||
172 8 0 0 0 2252 i2c.o
|
||||
80 12 0 8 0 202164 interrupt.o
|
||||
1244 204 246 12 0 267474 main.o
|
||||
1244 204 246 12 0 267470 main.o
|
||||
582 30 0 0 0 5481 pwm.o
|
||||
324 132 0 8 0 5521 retarget.o
|
||||
546 10 0 4120 0 211188 ssd1306.o
|
||||
|
|
@ -1191,7 +1194,7 @@ Image component sizes
|
|||
248 28 48 0 0 1988 uart.o
|
||||
|
||||
----------------------------------------------------------------------
|
||||
4830 642 648 4192 1024 754217 Object Totals
|
||||
4830 642 648 4192 1024 754213 Object Totals
|
||||
0 0 32 0 0 0 (incl. Generated)
|
||||
2 0 2 0 0 0 (incl. Padding)
|
||||
|
||||
|
|
@ -1257,8 +1260,8 @@ Image component sizes
|
|||
|
||||
Code (inc. data) RO Data RW Data ZI Data Debug
|
||||
|
||||
6176 698 688 4192 1120 750029 Grand Totals
|
||||
6176 698 688 2392 1120 750029 ELF Image Totals (compressed)
|
||||
6176 698 688 4192 1120 750025 Grand Totals
|
||||
6176 698 688 2392 1120 750025 ELF Image Totals (compressed)
|
||||
6176 698 688 2392 0 0 ROM Totals
|
||||
|
||||
==============================================================================
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -28,6 +28,26 @@ void EADC_FunctionTest(void);
|
|||
|
||||
|
||||
|
||||
void NRF24L01Init(){
|
||||
/* Set PB multi-function pins for spi RX*/
|
||||
SYS->GPC_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB7MFP_Msk);
|
||||
SYS->GPD_MFPL |= (SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 | SYS_GPB_MFPL_PB6MFP_SPI0_MISO0|SYS_GPB_MFPL_PB7MFP_SPI0_CLK);
|
||||
|
||||
SYS->GPC_MFPH &= ~(SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk);
|
||||
SYS->GPD_MFPL |= (SYS_GPB_MFPH_PB13MFP_GPIO | SYS_GPB_MFPL_PB6MFP_SPI0_MISO0|SYS_GPB_MFPL_PB7MFP_SPI0_CLK);
|
||||
|
||||
/* Set PC multi-function pins for PWM0 Channel0~3 */
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC0MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_PWM0_CH0;
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC1MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC1MFP_PWM0_CH1;
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC2MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC2MFP_PWM0_CH2;
|
||||
SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SYS_GPC_MFPL_PC3MFP_Msk));
|
||||
SYS->GPC_MFPL |= SYS_GPC_MFPL_PC3MFP_PWM0_CH3;
|
||||
|
||||
|
||||
}
|
||||
void PWMInit (){
|
||||
|
||||
CLK_EnableModuleClock(PWM0_MODULE);
|
||||
|
|
@ -80,6 +100,8 @@ void PWMInit (){
|
|||
// Start
|
||||
PWM_Start(PWM0, 0xF);
|
||||
}
|
||||
|
||||
|
||||
void I2CInit(){
|
||||
|
||||
/* Enable I2C0 module clock */
|
||||
|
|
@ -219,24 +241,17 @@ void EADC_FunctionTest()
|
|||
g_u32AdcIntFlag = 0;
|
||||
g_u32COVNUMFlag = 0;
|
||||
EADC_START_CONV(EADC, (0x1 << 7));
|
||||
|
||||
|
||||
/* Disable the sample module 7 interrupt */
|
||||
//EADC_DISABLE_SAMPLE_MODULE_INT(EADC, 0, (0x1 << 7));
|
||||
|
||||
/* Get the conversion result of the sample module */
|
||||
for(u32SAMPLECount = 0; u32SAMPLECount < 4; u32SAMPLECount++)
|
||||
i32ConversionData[u32SAMPLECount] = EADC_GET_CONV_DATA(EADC, (u32SAMPLECount + 4));
|
||||
|
||||
x = EADC_GET_DATA_VALID_FLAG(EADC, 0xF0);
|
||||
/* Wait conversion done */
|
||||
while(EADC_GET_DATA_VALID_FLAG(EADC, 0xF0) != 0xF0){
|
||||
x = EADC_GET_DATA_VALID_FLAG(EADC, 0xF0);
|
||||
x++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
/* Get the conversion result of the sample module */
|
||||
for(u32SAMPLECount = 4; u32SAMPLECount < 8; u32SAMPLECount++)
|
||||
i32ConversionData[u32SAMPLECount] = EADC_GET_CONV_DATA(EADC, u32SAMPLECount);
|
||||
|
|
@ -247,8 +262,6 @@ void EADC_FunctionTest()
|
|||
print_Line(0, dat);
|
||||
for(g_u32COVNUMFlag = 0; (g_u32COVNUMFlag) < 8; g_u32COVNUMFlag++)
|
||||
printf("Conversion result of channel %d: 0x%X (%d)\n", (g_u32COVNUMFlag % 4), i32ConversionData[g_u32COVNUMFlag], i32ConversionData[g_u32COVNUMFlag]);
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -143,56 +143,7 @@
|
|||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M451_AP_256 -FS00 -FL040000 -FP0($$Device:M451VG6AE$Flash\M451_AP_256.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>81</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>5792</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\main.cpp</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\steper\main.cpp\81</Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>1</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>78</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>5772</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\main.cpp</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\steper\main.cpp\78</Expression>
|
||||
</Bp>
|
||||
<Bp>
|
||||
<Number>2</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>77</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>5762</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>.\main.cpp</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\steper\main.cpp\77</Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
|
|
|
|||
Loading…
Reference in New Issue